NVMe

Model dual NVMe conencted to PCIe and receiving requests from a Host

NVMe_Controller_V3

Browsable image of the model.

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NVMe_Controller_V3model <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Bytes\t= 128.0\\ninput.A_Source\t= &quot;Host_2&quot;\\ninput.A_Destination = &quot;SSD2&quot;\\ninput.A_Priority = irand(1,5)\\ninput.A_Task_Flag\t= true\\nRead_Write\t= irand(1,100)\\ninput.A_Command\t= (Read_Write &lt;= 50)?&quot;Read&quot;:&quot;Write&quot;\t</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Bytes\t= 128.0\\ninput.A_Source\t= &quot;Host_2&quot;\\ninput.A_Destination = &quot;SSD2&quot;\\ninput.A_Priority = irand(1,5)\\ninput.A_Task_Flag\t= true\\nRead_Write\t= irand(1,100)\\ninput.A_Command\t= (Read_Write &lt;= 50)?&quot;Read&quot;:&quot;Write&quot;\t</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Bytes\t= 128.0\\ninput.A_Source\t= &quot;Host_1&quot;\\ninput.A_Destination = &quot;SSD&quot;\\ninput.A_Priority = irand(1,5)\\ninput.A_Task_Flag\t= true\\nRead_Write\t= irand(1,100)\\ninput.A_Command\t= (Read_Write &lt;= 50)?&quot;Read&quot;:&quot;Write&quot;\t</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Bytes\t= 128.0\\ninput.A_Source\t= &quot;Host_1&quot;\\ninput.A_Destination = &quot;SSD&quot;\\ninput.A_Priority = irand(1,5)\\ninput.A_Task_Flag\t= true\\nRead_Write\t= irand(1,100)\\ninput.A_Command\t= (Read_Write &lt;= 50)?&quot;Read&quot;:&quot;Write&quot;\t</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>SSD2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sequence_Read_Time</td><td>5.0e-9</td><td>5.0E-9</td></tr><tr><td>Random_Read_Time</td><td>5.0e-9</td><td>5.0E-9</td></tr><tr><td>Write_Access</td><td>5.0e-9</td><td>5.0E-9</td></tr><tr><td>Arch_Setup</td><td>Arch_Setup</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Page_Size</td><td>2048</td><td>2048</td></tr><tr><td>Erase_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Read_Access_Time</td><td>5.0e-9</td><td>5.0E-9</td></tr><tr><td>Write_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Erase_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Flash_Name</td><td>&quot;SSD2&quot;</td><td>&quot;SSD2&quot;</td></tr><tr><td>Flash_CTRL_Name</td><td>&quot;Flash_Ctrl2&quot;</td><td>&quot;Flash_Ctrl2&quot;</td></tr></table> <h2>NVMe2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Number_Of_Cores</td><td>10</td><td>10</td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>0.5</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>View_Report</td><td>true</td><td>true</td></tr><tr><td>Number_Of_Stats_Samples</td><td>5</td><td>5</td></tr><tr><td>Save_Report</td><td>false</td><td>false</td></tr><tr><td>NVMe_Instance</td><td>&quot;NVMe_2&quot;</td><td>&quot;NVMe_2&quot;</td></tr><tr><td>SSD_Connected</td><td>&quot;SSD2&quot;</td><td>&quot;SSD2&quot;</td></tr></table> <h2>Latency2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>Write_Latency,Read_Latency</td><td>Write_Latency,Read_Latency</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>ExpressionList4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A\t= (input.A_Command == &quot;Write&quot;)?true:false\\n\\nLatency\t= TNow - input.TIME</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A\t= (input.A_Command == &quot;Write&quot;)?true:false\\n\\nLatency\t= TNow - input.TIME</td></tr><tr><td>Output_Ports</td><td>output,output1</td><td>&quot;output,output1&quot;</td></tr><tr><td>Output_Values</td><td>Latency,Latency</td><td>&quot;Latency,Latency&quot;</td></tr><tr><td>Output_Conditions</td><td>Result_A,!Result_A</td><td>&quot;Result_A,!Result_A&quot;</td></tr></table> <h2>DeviceInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Host_2&quot;</td><td>&quot;Host_2&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>Traffic2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>10.0e-5</td><td>1.0E-4</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A\t= (input.A_Command == &quot;Write&quot;)?true:false\\n\\nLatency\t= TNow - input.TIME</td><td>/* Template to enter multiple RegEx lines*/\\nResult_A\t= (input.A_Command == &quot;Write&quot;)?true:false\\n\\nLatency\t= TNow - input.TIME</td></tr><tr><td>Output_Ports</td><td>output,output1</td><td>&quot;output,output1&quot;</td></tr><tr><td>Output_Values</td><td>Latency,Latency</td><td>&quot;Latency,Latency&quot;</td></tr><tr><td>Output_Conditions</td><td>Result_A,!Result_A</td><td>&quot;Result_A,!Result_A&quot;</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>Write_Latency,Read_Latency</td><td>Write_Latency,Read_Latency</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>SSD</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sequence_Read_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Random_Read_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Write_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Arch_Setup</td><td>Arch_Setup</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Page_Size</td><td>2048</td><td>2048</td></tr><tr><td>Erase_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Read_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Write_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Erase_Access_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Flash_Name</td><td>&quot;SSD&quot;</td><td>&quot;SSD&quot;</td></tr><tr><td>Flash_CTRL_Name</td><td>&quot;Flash_Ctrl&quot;</td><td>&quot;Flash_Ctrl&quot;</td></tr></table> <h2>DeviceInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Host_1&quot;</td><td>&quot;Host_1&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>PCIe_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_1&quot;</td><td>&quot;PCIe_1&quot;</td></tr><tr><td>Number_of_Lanes</td><td>2 /* Can be an array */</td><td>2</td></tr><tr><td>Slave_Buffer</td><td>512  /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512  /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>0.5</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16  /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12}  /* Master, Endpoint  Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64 /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128  /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0  /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0  /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6  /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2  /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_4  /* Per Lane */</td><td>1969.2</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5  /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;SSD&quot;},{&quot;SSD2&quot;},{&quot;DRAM_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;}}</td><td>{{&quot;SSD&quot;}, {&quot;SSD2&quot;}, {&quot;DRAM_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                  */\\nSource_Node  Destination_Node  Hop       Source_Port ; \\nProcessor_1  Cache_1           Port_1    output      ; \\nCache_1      Processor_1       Port_2    output      ; \\nCache_1      SDRAM_1           Port_2    output      ; \\nSDRAM_1      Cache_1           Port_4    output      ; \\nSDRAM_1      Processor_1       Port_4    output      ; \\n</td><td>/* First row contains Column Names.                  */\\nSource_Node  Destination_Node  Hop       Source_Port ; \\nProcessor_1  Cache_1           Port_1    output      ; \\nCache_1      Processor_1       Port_2    output      ; \\nCache_1      SDRAM_1           Port_2    output      ; \\nSDRAM_1      Cache_1           Port_4    output      ; \\nSDRAM_1      Processor_1       Port_4    output      ; \\n</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>All</td><td>All</td></tr></table> <h2>Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>10.0e-5</td><td>1.0E-4</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>NVMe</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Number_Of_Cores</td><td>10</td><td>10</td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>0.5</td></tr><tr><td>_hideName</td><td>true</td><td>true</td></tr><tr><td>View_Report</td><td>true</td><td>true</td></tr><tr><td>Number_Of_Stats_Samples</td><td>5</td><td>5</td></tr><tr><td>Save_Report</td><td>false</td><td>false</td></tr><tr><td>NVMe_Instance</td><td>&quot;NVMe_1&quot;</td><td>&quot;NVMe_1&quot;</td></tr><tr><td>SSD_Connected</td><td>&quot;SSD&quot;</td><td>&quot;SSD&quot;</td></tr></table>

"Today’s processing is very data dependent. This means that the processing core is no longer the bottleneck. With the addition of multi-core there is significant trade-off and reduction available cache. In the past, hit-ratios were used to measure the performance of the system and MIPS was the final throughput number. Video processing and multi-media applications have left these metrics in the dust. At the same time, they have also caused a lot of confusion in what the metrics should be. Solid State Devices or SSD have been considered to be a solution for power reduction.

SSD, by itself, does not offer any power reduction, per se. A 7500 rpm 2.5” drive actually offers better power numbers compared to the best SSD. The advantage is the reduced usage of the cores and other devices that consume are idle more often and consume lower power.

There is a profound difference in performance and power depending on the product architecture and design. Drives consume < 5% of the total power. So, even the most power-saver will increase battery life by 10 min. The difference is in what it does with the other devices.

This is where more effort at the architecture definition phase becomes very valuable. Architecture or System models provide a means of exploring the performance and power consumption of a system for a large variety of scenarios. These are simulation models built early in the design cycle and prior to the specification is formalized. Unlike hardware prototypes, the models can be easily refined based on the simulation results. Also, ad-hoc studies such as the addition of a processor or a new application be quickly studied, sometimes even of the software is not available. A variety of analysis that are not possible with hardware prototypes such as processor stall times, or the number of IO/s or the MB/s of data accessed from the SSD.

#powerreduction, #SSD, #NVMe, #multicore #powergating"