Full SoC

GPU, Big-Little with A72 and A53 and TI C6X core

Semiconductors

  • Full SoC
    GPU, Big-Little with A72 and A53 and TI C6X core
  • Processor
    Modeling a processor pipeline
  • Multimedia SoC
    Exploring the implementation of a real-time video processing on a ARM SoC with hardware accelerators and power management

MultiSoC

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MultiSoCmodel <h2>ExpressionList4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\n Result_A = (TNow - input.TIME)/2.5e-9</td><td>/* Template to enter multiple RegEx lines*/\\n Result_A = (TNow - input.TIME)/2.5e-9</td></tr><tr><td>Output_Ports</td><td>output,output1,output2,output3</td><td>&quot;output,output1,output2,output3&quot;</td></tr><tr><td>Output_Values</td><td>Result_A,Result_A,Result_A,Result_A</td><td>&quot;Result_A,Result_A,Result_A,Result_A&quot;</td></tr><tr><td>Output_Conditions</td><td>(input.A_Destination==&quot;MM&quot;),(input.A_Destination==&quot;TG2&quot;),(input.A_Destination==&quot;TG3&quot;),(input.A_Destination==&quot;TG4&quot;)</td><td>&quot;(input.A_Destination==&quot;MM&quot;),(input.A_Destination==&quot;TG2&quot;),(input.A_Destination==&quot;TG3&quot;),(input.A_Destination==&quot;TG4&quot;)&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>SingleEvent</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_explanation</td><td>Source-&gt;Event-&gt;SingleEvent\t</td><td>Source-&gt;Event-&gt;SingleEvent\t</td></tr><tr><td>time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>value</td><td>true</td><td>true</td></tr></table> <h2>Create_Statistics</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Statistic_Name</td><td>&quot;Statistic_Name&quot;</td><td>&quot;Statistic_Name&quot;</td></tr><tr><td>Sample_Every_Nth_DS</td><td>1</td><td>1</td></tr><tr><td>Batch_Count_Min_Max</td><td>&quot;1 0.0 TStop&quot;</td><td>&quot;1 0.0 TStop&quot;</td></tr></table> <h2>Crossbar</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>PowerTable</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td></tr><tr><td>Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Manager_Setup</td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n where &quot;Scheduler_&quot; or &quot;STR_&quot; + BlockName; Processor, Bus, DRAM = Architecture_Name + &quot;_&quot; + BlockName \\n--------Device Name------- ---------Power States------ -----Operating States------ --toActive-- --Speed-- --Exist-- */\\nArchitecture_Block Standby Active Wait Idle Refresh Existing OffState OnState t_OnOff Mhz Volts ; \\nArchitecture_1_C64 70.0 300.0 0.0 0.0 0.0 Standby Standby Active Cycle_t 1000.0 1.0 ; \\nArchitecture_1_DRAM 70.0 300.0 0.0 0.0 100.0 Standby Standby Active 0.0 1000.0 1.0 ; \\n</td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n where &quot;Scheduler_&quot; or &quot;STR_&quot; + BlockName; Processor, Bus, DRAM = Architecture_Name + &quot;_&quot; + BlockName \\n--------Device Name------- ---------Power States------ -----Operating States------ --toActive-- --Speed-- --Exist-- */\\nArchitecture_Block Standby Active Wait Idle Refresh Existing OffState OnState t_OnOff Mhz Volts ; \\nArchitecture_1_C64 70.0 300.0 0.0 0.0 0.0 Standby Standby Active Cycle_t 1000.0 1.0 ; \\nArchitecture_1_DRAM 70.0 300.0 0.0 0.0 100.0 Standby Standby Active 0.0 1000.0 1.0 ; \\n</td></tr><tr><td>Async_State_Change</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n where State to same State can extend a Power State \\n--------Device Name------- --Start------Expression------Next--- */\\nArchitecture_Block State Time State ; \\n</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n where State to same State can extend a Power State \\n--------Device Name------- --Start------Expression------Next--- */\\nArchitecture_Block State Time State ; \\n</td></tr><tr><td>Expression_List</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- --------------Expression------------ */\\nName Value ; \\nCycle_t 1.0E-6 / Mhz ; \\n</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- --------------Expression------------ */\\nName Value ; \\nCycle_t 1.0E-6 / Mhz ; \\n</td></tr><tr><td>Battery_Units</td><td>Milli_Watts</td><td>Milli_Watts</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>LPDDR Statistics</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>LPDDR Statistics</td><td>LPDDR Statistics</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>HW_DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR&quot;</td><td>&quot;DDR&quot;</td></tr><tr><td>HW_DRAM_Speed_Mhz</td><td>400.0</td><td>400.0</td></tr><tr><td>Number_of_Banks</td><td>8</td><td>8</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td></tr><tr><td>Memory_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Burst_Length</td><td>8 /* 2, 4, 8 */</td><td>8</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR3&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR3&quot;</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{3,7,8,17} /* tCL, tRCD, tRP, tRAS */</td><td>{3, 7, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>{1,3,4,1,3,1,1} /* DQSS, tWTR, tRRD, tWR, tRL, tWL , tDQSCK*/</td><td>{1, 3, 4, 1, 3, 1, 1}</td></tr><tr><td>Fix_DQSS</td><td>true</td><td>true</td></tr><tr><td>Refresh_Rate_per_Bank_ms</td><td>64.0 /* 64.0 ms */</td><td>64.0</td></tr><tr><td>Refresh_Cycles_per_Bank</td><td>256 /* 256 cycles per bank */</td><td>256</td></tr><tr><td>Enable_External_Data</td><td>false</td><td>false</td></tr><tr><td>Address_Bit_Map</td><td>{{0,9},{10,24},{25,27}} /* col, row, bank (min, max) Bit Position */</td><td>{{0, 9}, {10, 24}, {25, 27}}</td></tr><tr><td>Standard_Name</td><td>&quot;none&quot; /*reads DDR_Memory_Standards.txt */</td><td>&quot;none&quot;</td></tr><tr><td>Standard_File</td><td>VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt</td><td>&quot;VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Memory_Controller</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Bank_at_a_Time</td><td>true /* false=all */</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr><tr><td>Path</td><td>&quot;VS/User_Library&quot;</td><td>&quot;VS/User_Library&quot;</td></tr></table> <h2>Memory_Controller</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Controller_Name</td><td>&quot;LPDDR3&quot;</td><td>&quot;LPDDR3&quot;</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR3&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR3&quot;</td></tr><tr><td>Controller_Speed_Mhz</td><td>1200.0</td><td>1200.0</td></tr><tr><td>Memory_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Bus_Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Command_Buffer_Length</td><td>15</td><td>15</td></tr><tr><td>Commands_in_a_Row</td><td>0</td><td>0</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{3,7,8,17} /* tCL, tRCD, tRP, tRAS */</td><td>{3, 7, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>{1,3,4,1,3,1,1,1,0} /* DQSS, tWTR, tRRD,tWR, tRL, tWL, tDQSCK, tRTP, tHWpre */</td><td>{1, 3, 4, 1, 3, 1, 1, 1, 0}</td></tr><tr><td>Burst_Length</td><td>8 /* 2, 4, 8 */</td><td>8</td></tr><tr><td>Memory_Column</td><td>{0,9} </td><td>{0, 9}</td></tr><tr><td>Memory_Row</td><td>{13,25}</td><td>{13, 25}</td></tr><tr><td>Memory_Bank</td><td>{10,12}</td><td>{10, 12}</td></tr><tr><td>Memory_Bank_Length</td><td>round(pow(2,(Memory_Bank(1) - Memory_Bank(0) + 1)))</td><td>8L</td></tr><tr><td>DRAM_Return_Cycles</td><td>0</td><td>0</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;DDR&quot;</td><td>&quot;DDR&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot; /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Input_Device_Name</td><td>&quot;AXI_DRAM&quot;</td><td>&quot;AXI_DRAM&quot;</td></tr></table> <h2>TG_AXI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Bus_Speed</td><td>400.0</td><td>400.0</td></tr><tr><td>Device_Name</td><td>&quot;MM&quot;</td><td>&quot;MM&quot;</td></tr><tr><td>Destination_Name</td><td>&quot;DDR&quot;</td><td>&quot;DDR&quot;</td></tr><tr><td>Traffic_Rate_Mhz</td><td>200.0</td><td>200.0</td></tr><tr><td>Data_Size</td><td>AXI_Burst_Length</td><td>32</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>Bus_Name</td><td>Device_Name + &quot;_AXI&quot;</td><td>&quot;MM_AXI&quot;</td></tr><tr><td>Read_Write</td><td>&quot;Read&quot;</td><td>&quot;Read&quot;</td></tr><tr><td>Addr_Start</td><td>0</td><td>0</td></tr><tr><td>Priority</td><td>1</td><td>1</td></tr></table> <h2>DRAM3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM_DSP&quot;</td><td>&quot;DRAM_DSP&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>2000.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 1.0, Prefetch 6.0, Write 1.0, ReadWrite 4.0, Erase 9.0&quot;</td><td>&quot;Read 1.0, Prefetch 6.0, Write 1.0, ReadWrite 4.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>DDR3</td><td>DDR3</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ARM_A53</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Processor_Speed</td><td>Processor_Speed/2.0</td><td>400.0</td></tr><tr><td>I_Cache_Size</td><td>I_Cache_Size</td><td>8</td></tr><tr><td>D_Cache_Size</td><td>D_Cache_Size</td><td>16</td></tr><tr><td>Bus_Speed</td><td>Bus_Speed/2.0</td><td>1000.0</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>Cluster_Name</td><td>&quot;Cluster_2&quot;</td><td>&quot;Cluster_2&quot;</td></tr><tr><td>Num_Cores</td><td>Num_Cores</td><td>5</td></tr><tr><td>Burst_Size</td><td>Burst_Size</td><td>100</td></tr></table> <h2>ARM_A72</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Processor_Speed</td><td>Processor_Speed</td><td>800.0</td></tr><tr><td>I_Cache_Size</td><td>I_Cache_Size</td><td>8</td></tr><tr><td>D_Cache_Size</td><td>D_Cache_Size</td><td>16</td></tr><tr><td>Bus_Speed</td><td>Bus_Speed</td><td>2000.0</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>Cluster_Name</td><td>&quot;Cluster_1&quot;</td><td>&quot;Cluster_1&quot;</td></tr><tr><td>Num_Cores</td><td>Num_Cores</td><td>5</td></tr><tr><td>Burst_Size</td><td>Burst_Size</td><td>100</td></tr><tr><td>Bus_Pwr_Name</td><td>&quot;Architecture_1_&quot; + &quot;Bus_1&quot;+Cluster_Name</td><td>&quot;Architecture_1_Bus_1Cluster_1&quot;</td></tr><tr><td>L3_Pwr_Name</td><td>&quot;Architecture_1_&quot; + &quot;L3&quot; + Cluster_Name</td><td>&quot;Architecture_1_L3Cluster_1&quot;</td></tr><tr><td>AXI_RD_Pwr</td><td>&quot;STR_&quot; + &quot;AXI_&quot; + Cluster_Name+ &quot;_Rd_Data_Channel&quot;</td><td>&quot;STR_AXI_Cluster_1_Rd_Data_Channel&quot;</td></tr><tr><td>AXI_WR_Pwr</td><td>&quot;STR_&quot; + &quot;AXI_&quot; + Cluster_Name + &quot;_Wr_Data_Channel&quot;</td><td>&quot;STR_AXI_Cluster_1_Wr_Data_Channel&quot;</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Destination = &quot;C64&quot;\\ninput.A_Hop = &quot;C64&quot;\\ninput.A_Variables = 3000\\ninput.TIME = TNow</td><td>input.A_Destination = &quot;C64&quot;\\ninput.A_Hop = &quot;C64&quot;\\ninput.A_Variables = 3000\\ninput.TIME = TNow</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>AMBA_AXI6</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_DSP&quot;</td><td>&quot;AXI_DSP&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>400.0</td><td>400.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>2.5E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>1</td><td>1</td></tr><tr><td>Number_Slaves</td><td>1</td><td>1</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{400.0, 400.0, 400.0, 400.0, 400.0, 400.0, 400.0, 400.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DRAM&quot;,&quot;DRAM_DSP&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;DRAM&quot;, &quot;DRAM_DSP&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false} </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>Traffic3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>0.0</td><td>0.0</td></tr><tr><td>Value_1</td><td>Sim_Time /15.0</td><td>1.0E-5</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>SoftGen2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;SoftGen_DSP&quot;</td><td>&quot;SoftGen_DSP&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Random&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Random&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr><tr><td>Instruction_Mix_File</td><td>C64_Instr_Mix.txt</td><td>&quot;C64_Instr_Mix.txt&quot;</td></tr></table> <h2>TMS320C</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;C64&quot;</td><td>&quot;C64&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ; \\nProcessor_Instruction_Set: C64_Instr \\nNumber_of_Registers: 64 \\nProcessor_Speed_Mhz: DSP_Speed \\nContext_Switch_Cycles: 300 \\nInstruction_Queue_Length: 8 \\nInstructions_per_Cycle:\t\t 8 \\nNumber_of_Pipeline_Stages: 5 \\nNumber_of_INT_Execution_Units: 8 \\nNumber_of_FP_Execution_Units: 0 \\nNumber_of_Cache_Execution_Units: 3 \\nI_1: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=16.0, Words_per_Cache_Access=8, Hit_Ratio=100, Words_per_Cache_Line=128, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=16.0, Words_per_Cache_Access=8, Hit_Ratio=100, Words_per_Cache_Line=128, Cache_Miss_Name=L2} \\nL2: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=256.0, Words_per_Cache_Access=8, Words_per_Cache_Line=128, Cache_Miss_Name=DRAM_DSP} </td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ; \\nProcessor_Instruction_Set: C64_Instr \\nNumber_of_Registers: 64 \\nProcessor_Speed_Mhz: DSP_Speed \\nContext_Switch_Cycles: 300 \\nInstruction_Queue_Length: 8 \\nInstructions_per_Cycle:\t\t 8 \\nNumber_of_Pipeline_Stages: 5 \\nNumber_of_INT_Execution_Units: 8 \\nNumber_of_FP_Execution_Units: 0 \\nNumber_of_Cache_Execution_Units: 3 \\nI_1: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=16.0, Words_per_Cache_Access=8, Hit_Ratio=100, Words_per_Cache_Line=128, Cache_Miss_Name=L2} \\nD_1: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=16.0, Words_per_Cache_Access=8, Hit_Ratio=100, Words_per_Cache_Line=128, Cache_Miss_Name=L2} \\nL2: {Cache_Speed_Mhz=DSP_Speed, Size_KBytes=256.0, Words_per_Cache_Access=8, Words_per_Cache_Line=128, Cache_Miss_Name=DRAM_DSP} </td></tr><tr><td>Pipeline_Stages</td><td>/* First row contains Column Names. */\\nStage_Name Execution_Location Action Condition ; \\n1_PREFETCH I_1 instr none ; \\n2_DECODE I_1 wait none ; \\n3_DATAOPER D_1 read none ;\\n4_EXECUTE DSP exec none ;\\n5_STORE DSP wait none ;\\n5_STORE D_1 \t write none ;</td><td>/* First row contains Column Names. */\\nStage_Name Execution_Location Action Condition ; \\n1_PREFETCH I_1 instr none ; \\n2_DECODE I_1 wait none ; \\n3_DATAOPER D_1 read none ;\\n4_EXECUTE DSP exec none ;\\n5_STORE DSP wait none ;\\n5_STORE D_1 \t write none ;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table> <h2>DeviceInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Display&quot;</td><td>&quot;Display&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Delay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Delay_Value</td><td>100.0e-9</td><td>&quot;100.0e-9&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>0</td><td>0</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Task_Name = &quot;Display_Task&quot;\\ninput.A_Source = &quot;Trigger&quot;\\ninput.A_Instruction = (rand(0.0,1.0)&gt; 0.5)?{&quot;Store&quot;}:{&quot;Load&quot;}</td><td>input.A_Task_Name = &quot;Display_Task&quot;\\ninput.A_Source = &quot;Trigger&quot;\\ninput.A_Instruction = (rand(0.0,1.0)&gt; 0.5)?{&quot;Store&quot;}:{&quot;Load&quot;}</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>Traffic2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>1.0E-9</td><td>1.0E-9</td></tr><tr><td>Value_1</td><td>1.0E-6</td><td>1.0E-6</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>DeviceInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Trigger&quot;</td><td>&quot;Trigger&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>DMADatabase</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase1&quot;</td><td>&quot;DMADatabase1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\nDisplay_Task Load\t 0\t Display\t 32\t 1 Read\t 200\t 0\t DMA \\nDisplay_Task Store\t 0\t DRAM\t \t 32\t 2 Write\t 150\t 0\t DMA \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\nDisplay_Task Load\t 0\t Display\t 32\t 1 Read\t 200\t 0\t DMA \\nDisplay_Task Store\t 0\t DRAM\t \t 32\t 2 Write\t 150\t 0\t DMA \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase1&quot;</td><td>&quot;DMADatabase1&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>10</td><td>&quot;10&quot;</td></tr><tr><td>Speed_Mhz</td><td>Bus_Speed</td><td>&quot;Bus_Speed&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr></table> <h2>Bridge6</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge_IO&quot;</td><td>&quot;Bridge_IO&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>500.0</td><td>500.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>0</td><td>0</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>AMBA_AXI5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_IO&quot;</td><td>&quot;AXI_IO&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>1</td><td>1</td></tr><tr><td>Number_Slaves</td><td>1</td><td>1</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Display&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Display&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false} </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>AMBA_AXI4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_IO_INTF&quot;</td><td>&quot;AXI_IO_INTF&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>3</td><td>3</td></tr><tr><td>Number_Slaves</td><td>2</td><td>2</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DRAM&quot;,&quot;DDR&quot;},{&quot;Display&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;DRAM&quot;, &quot;DDR&quot;}, {&quot;Display&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false} </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>Bridge5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge_Core&quot;</td><td>&quot;Bridge_Core&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>500.0</td><td>500.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>0</td><td>0</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>Bridge3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bridge_Name</td><td>&quot;Bridge_DSP&quot;</td><td>&quot;Bridge_DSP&quot;</td></tr><tr><td>Bridge_Speed_in_Mhz</td><td>Bus_Speed</td><td>2000.0</td></tr><tr><td>Bridge_Width_in_Bytes</td><td>4</td><td>4</td></tr><tr><td>Overhead_Cycles</td><td>0</td><td>0</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Bridge</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>Instr_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;C64_Instr&quot;</td><td>&quot;C64_Instr&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n DSP LUnit MUnit SUnit DUnit ;\\n LUnit INT_1 INT_2 \t\t;\\n MUnit INT_3 INT_4 \t;\\n SUnit INT_5 INT_6 \t;\\n DUnit INT_7 INT_8\t\t\t;\\n\\nbegin INT_7 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV 1 ;\\nOR 1 ;\\nSTB 1 ;\\nLDB 5 ;\\nSUB 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_7 ;\\n\\nbegin INT_8 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV 1 ;\\nOR 1 ;\\nSTB 1 ;\\nLDB 5 ;\\nSUB 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_8 ;\\n\\nbegin INT_3 ; /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL 2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD 4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend INT_3 ;\\n\\nbegin INT_4 ; /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL 2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD 4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend INT_4 ;\\n\\nbegin INT_5 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B 5 ;\\nDMV 1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL 1 ;\\nMV 1 ;\\nSHR 1 ; \\nNEG 1 ;\\nOR 1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_5 ;\\n\\nbegin INT_6 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B 5 ;\\nDMV 1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL 1 ;\\nMV 1 ;\\nSHR 1 ; \\nNEG 1 ;\\nOR 1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_6 ;\\n\\nbegin INT_1 ; /* Group */\\nADD 1 ;\\nABS 1 ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV 1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT 1 ; \\nOR 1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nLMBD 1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\nADD 1 ;\\nABS 1 ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV 1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT 1 ; \\nOR 1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nLMBD 1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend INT_2 ;</td><td>/* Instruction Set or File Path. */\\n Mnew Ra Rb Rc Rd Re ; /* Label */\\n DSP LUnit MUnit SUnit DUnit ;\\n LUnit INT_1 INT_2 \t\t;\\n MUnit INT_3 INT_4 \t;\\n SUnit INT_5 INT_6 \t;\\n DUnit INT_7 INT_8\t\t\t;\\n\\nbegin INT_7 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV 1 ;\\nOR 1 ;\\nSTB 1 ;\\nLDB 5 ;\\nSUB 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_7 ;\\n\\nbegin INT_8 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\nMV 1 ;\\nOR 1 ;\\nSTB 1 ;\\nLDB 5 ;\\nSUB 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_8 ;\\n\\nbegin INT_3 ; /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL 2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD 4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend INT_3 ;\\n\\nbegin INT_4 ; /* Group */\\nAVG 2 ;\\nMPY 1 ;\\nSSHVL 2 ;\\nBIT 2 ;\\nXORMPY 4 ;\\nXPND 2 ;\\nCMPY 3 ;\\nDDOTP 4 ;\\nDEAL 2 ;\\nMVD 4 ;\\nROTL 2 ;\\nSHFL 2 ;\\nend INT_4 ;\\n\\nbegin INT_5 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B 5 ;\\nDMV 1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL 1 ;\\nMV 1 ;\\nSHR 1 ; \\nNEG 1 ;\\nOR 1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_5 ;\\n\\nbegin INT_6 ; /* Group */\\nADD 1 ;\\nAND 1 ;\\n*B 5 ;\\nDMV 1 ;\\nSET 1 ;\\nMIN 1 ;\\nSHL 1 ;\\nMV 1 ;\\nSHR 1 ; \\nNEG 1 ;\\nOR 1 ;\\nPACK 1 ;\\nSUB 1 ;\\nCLR 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU4 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nend INT_6 ;\\n\\nbegin INT_1 ; /* Group */\\nADD 1 ;\\nABS 1 ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV 1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT 1 ; \\nOR 1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nLMBD 1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend INT_1 ;\\n\\nbegin INT_2 ; /* Group */\\nADD 1 ;\\nABS 1 ;\\nAND 1 ;\\nMIN 1 ; \\nSHL 1 ;\\nMV 1 ;\\nSUB 1 ;\\nNEG 1 ;\\nNORM 1 ;\\nNOT 1 ; \\nOR 1 ;\\nPACK 1 ;\\nCMP 1 ;\\nSWAP 1 ;\\nUNPKHU 1 ;\\nXOR 1 ;\\nZERO 1 ;\\nLMBD 1 ;\\nSAT 1 ;\\nMAX 1 ;\\nend INT_2 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name2&quot;</td><td>&quot;Record_Set_Name2&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>AMBA_AXI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_DRAM&quot;</td><td>&quot;AXI_DRAM&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>16</td><td>16</td></tr><tr><td>Number_Slaves</td><td>8</td><td>8</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;DRAM&quot;},{&quot;Device_2&quot;},{&quot;DRAM1&quot;},{&quot;Device_4&quot;},{&quot;DDR&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;DRAM_DSP&quot;}}</td><td>{{&quot;DRAM&quot;}, {&quot;Device_2&quot;}, {&quot;DRAM1&quot;}, {&quot;Device_4&quot;}, {&quot;DDR&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;DRAM_DSP&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false} </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr><tr><td>Sim_Time</td><td>Sim_Time</td><td>1.5E-4</td></tr></table> <h2>Database2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;TLB&quot;</td><td>&quot;TLB&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>Cluster\t\tA_Prefetch_Name\t\tA_Destination\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tL2\t\t\tL3Cluster1\\nCluster_1\tL2\t\t\tL3Cluster1\\nCluster_1\tL2\t\t\tL3Cluster1\\n\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tL2\t\t\tL3Cluster2\\nCluster_2\tL2\t\t\tL3Cluster2\\nCluster_2\tL2\t\t\tL3Cluster2</td><td>Cluster\t\tA_Prefetch_Name\t\tA_Destination\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tI_1\t\t\tDRAM\\nCluster_1\tL2\t\t\tL3Cluster1\\nCluster_1\tL2\t\t\tL3Cluster1\\nCluster_1\tL2\t\t\tL3Cluster1\\n\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tI_1\t\t\tDRAM\\nCluster_2\tL2\t\t\tL3Cluster2\\nCluster_2\tL2\t\t\tL3Cluster2\\nCluster_2\tL2\t\t\tL3Cluster2</td></tr><tr><td>Input_Fields</td><td>&quot;Cluster, A_Prefetch_Name&quot;</td><td>&quot;Cluster, A_Prefetch_Name&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;Cluster, A_Prefetch_Name&quot;</td><td>&quot;Cluster, A_Prefetch_Name&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;input.A_Destination = match.A_Destination&quot; /* FORMAT output = match.fieldb */</td><td>&quot;input.A_Destination = match.A_Destination&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>DRAM2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM1&quot;</td><td>&quot;DRAM1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>500.0</td><td>500.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 2.0, Prefetch 6.0, Write 2.0, ReadWrite 4.0, Erase 9.0&quot;</td><td>&quot;Read 2.0, Prefetch 6.0, Write 2.0, ReadWrite 4.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\t\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\n\\n\\nMy_Task_10Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_10 \\nMy_Task_20Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_10 \\nMy_Task_30Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_10 \\nMy_Task_11Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_11 \\nMy_Task_21Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_11 \\nMy_Task_31Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_11 \\n\\nMy_Task_12Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_12 \\nMy_Task_22Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_12 \\nMy_Task_32Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_12 \\nMy_Task_13Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_13 \\nMy_Task_23Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_13 \\nMy_Task_33Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_13\\nMy_Task_14Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_14 \\nMy_Task_24Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_14 \\nMy_Task_34Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_14 \\nMy_Task_15Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_15 \\nMy_Task_25Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_15 \\nMy_Task_35Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_15 \\n\\n\\nMy_Task_10Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_20 \\nMy_Task_20Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_20 \\nMy_Task_30Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_20 \\nMy_Task_11Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_21 \\nMy_Task_21Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_21 \\nMy_Task_31Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_21 \\n\\nMy_Task_12Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_22 \\nMy_Task_22Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_22 \\nMy_Task_32Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_22 \\nMy_Task_13Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_23 \\nMy_Task_23Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_23 \\nMy_Task_33Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_23\\nMy_Task_14Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_24 \\nMy_Task_24Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_24 \\nMy_Task_34Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_24 \\nMy_Task_15Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_25 \\nMy_Task_25Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_25 \\nMy_Task_35Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_25 \\n\\n</td><td>A_Task_Name\t\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address A_Command\tA_Bytes\tA_Priority\tA_Destination \\n\\n\\nMy_Task_10Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_10 \\nMy_Task_20Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_10 \\nMy_Task_30Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_10 \\nMy_Task_11Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_11 \\nMy_Task_21Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_11 \\nMy_Task_31Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_11 \\n\\nMy_Task_12Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_12 \\nMy_Task_22Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_12 \\nMy_Task_32Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_12 \\nMy_Task_13Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_13 \\nMy_Task_23Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_13 \\nMy_Task_33Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_13\\nMy_Task_14Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_14 \\nMy_Task_24Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_14 \\nMy_Task_34Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_14 \\nMy_Task_15Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_15 \\nMy_Task_25Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_15 \\nMy_Task_35Cluster_1\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_15 \\n\\n\\nMy_Task_10Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_20 \\nMy_Task_20Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_20 \\nMy_Task_30Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_20 \\nMy_Task_11Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_21 \\nMy_Task_21Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_21 \\nMy_Task_31Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_21 \\n\\nMy_Task_12Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_22 \\nMy_Task_22Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_22 \\nMy_Task_32Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_22 \\nMy_Task_13Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_23 \\nMy_Task_23Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_23 \\nMy_Task_33Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_23\\nMy_Task_14Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_24 \\nMy_Task_24Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_24 \\nMy_Task_34Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_24 \\nMy_Task_15Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Read\t 128\t0\t DMACluster_25 \\nMy_Task_25Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 1 Write\t128\t1\t DMACluster_25 \\nMy_Task_35Cluster_2\t LD_LDR\t 0\t DRAM1\t 32\t 2 Write\t128\t3\t DMACluster_25 \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC ; /* one execution unit */\\n EXEC INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n #LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC ; /* one execution unit */\\n EXEC INT_1 ; /* ARM execution unit */\\n\\nbegin INT_1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n #LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>2000.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 1.0, Prefetch 6.0, Write 1.0, ReadWrite 4.0, Erase 9.0&quot;</td><td>&quot;Read 1.0, Prefetch 6.0, Write 1.0, ReadWrite 4.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>DDR3</td><td>DDR3</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nC64 DRAM_DSP Bridge_DSP bus_out ;\\nDRAM_DSP C64 Bridge_DSP output ;\\n</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nC64 DRAM_DSP Bridge_DSP bus_out ;\\nDRAM_DSP C64 Bridge_DSP output ;\\n</td></tr><tr><td>Number_of_Samples</td><td>35</td><td>0</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;None&quot;</td><td>&quot;None&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table>

This models a large cluster of A72 and A53 with an AXI bus connection to the DRAM.

The semiconductor industry is driven by major technological advances. Semiconductors have become a part of Automotive, industrial sector, data processing application, consumer electronics, Artificial Intelligence/Machine Learning and IoT. Every product is determined by its performance, features, flexibility and power management. Using VisualSim, designers can perform performance analysis and architecture exploration methodology to gain extensive insight into the system operation. Architects and designers can analyze the cache hierarchy in an SoC to the application of a GPU in an ADAS design to FPGA in a data center.