Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
Processor Family
RISC-V SIMD RISC_V model execution the NP Benchmark tasks
PowerPC Network processor using a PowerPC. The backplane is a PCIe bus. The Processor, DMA and Switched Ethernet connected to the AXI Bus.
Coldfire Application of Coldfire in a Electronic Control Unit for a automotive application
RAD750 Implements the ARINC653 Time-Space RTOS running a set of tasks on the basic RAD750 with PCI, 1553B and SpaceWire interfaces.
Renesas SH4 ECU containing a SH4 running safety applications
Nvidia Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
SPARC and LEON Drive-PX modeled with a CAN Network that is sending 4 Radar signals and 2 camera signals. The Drive-PX is modeled with the 4 ARM A72, 2 Denver and the GPU
Intel ATOM Modeling a IoT application using an ATOm processor
AMD Opteron Compares the memory architecture of the Opteron Direct Connect with Xeon Shared Bus
TI OMAP Uses the OMAP4460 for a camera application
Drive_PX_SoC_GPU
Browsable image of the model.
To download OpenWebStart
click on the links - Windows- Compatibility:Windows 10 or higher (*) macOS - Compatibility:macOS 10.15 (Catalina) or higher (*) Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
For an executable version,
Mouse over the icons to view parameters. Click on hierarchy and plotters to reveal content (if provided).
To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
This is the skeleton of a Autonomous Driving application running on a Drive-PX platform from NVidia. There are two types of configurations:
6 radars delivering up to 15 targets each every 40ms cycle together with a front camera sending up to 15 objects every 40ms. All this data comes over the CAN (FD) busses.
Up to 6 cameras, one with 8Mpixels and the others with 1.5 Mpixels delivering the raw data to the Drive-PX. In addition 4 radars with up to 15 targets with a cycle time of 40ms.
This model evaluates different SW architectures. We need to measure memory usage, processor utilization, latency and throughput on the processors and the communication links depending on the distribution of tasks across the processors. Of course, the effects of errors will enlighten us on the robustness of a given architecture.