Cycle-accurate Memory

Modeling multiple requester with addresses to DDR and LPDDR

Cache Memory Storage

  • Architecture Cache
    Use of the Cache block as the L2 cache, receiving request from the I_1 and D_1 in the processor and a miss to a DRAM.
  • Cycle-Accurate Cache
    Modeling the cycle-accurate cache with 4-way associativity and snoop flag disabled.
  • Cache/Memory Hierarchy
    Shows an end-to-end operation with Processor core as a trace, 2 level cache, AXI bus, Memory Controller and DRAM
  • Architecture Memory
    Use of the Cache block as the L2 cache, receiving request from the I_1 and D_1 in the processor and a miss to a DRAM.
  • Cycle-accurate Memory
    Modeling multiple requester with addresses to DDR and LPDDR
  • Disk
    Host computer with SATA interface to a local disk drive
  • Hybrid Drive
    Multi-level drive with cache, SDRAM, flash and disk drive. Uses a ARM R8 for contorl processing
  • Flash
    Evaluate flash from different memory vendors by varying standard Flash parameters
  • SSD
    SSD using a generic Flash and a RISC-V for processing
  • Network-Attached Storage
    Modeling a video streaming server that is stored on a redundant NAS

Disk_Model6

Browsable image of the model.

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Disk_Model6model <h2>DISK_FIFO</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>SATA_FIFO</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Client_Arbiter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DRAM_Speed_Mhz</td><td>DRAM_Speed_Mhz</td><td>50.0</td></tr></table> <h2>Statistics</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Set_Flag</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Set_Threshold_Flag&quot;</td><td>&quot;Set_Threshold_Flag&quot;</td></tr><tr><td>Optional_Parameters</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value \\nPath none \\nRead_File none \\nSelf_Start false \\nParam_Script none \\nListen_to_File none \\nDuplicate_Input true \\nProfile 0 \\nProfile_File none \\nMaximum_Loops 1000000 \\nBlock_Reference Block_Name \\nPort_Order_Array {&quot;input&quot;} \\n</td></tr><tr><td>Self_Start</td><td>true</td><td>true</td></tr></table> <h2>VariableList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template \\nName Type Value */\\nSATA_Flag global 0 ;\\nDisk_Flag global 0 ;\\nThruput global 1 ; </td><td>/* Memory Initialize Template \\nName Type Value */\\nSATA_Flag global 0 ;\\nDisk_Flag global 0 ;\\nThruput global 1 ; </td></tr></table> <h2>SATA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>Disk</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Priority</td><td>3</td><td>3</td></tr><tr><td>Block_Size</td><td>512</td><td>512</td></tr><tr><td>Starting_Zone</td><td>1</td><td>1</td></tr><tr><td>Zone_Change_Prob</td><td>1.0</td><td>1.0</td></tr><tr><td>Inter_Block_Time</td><td>800.0e-9</td><td>8.0E-7</td></tr><tr><td>Seek_Latency</td><td>100.0e-9</td><td>1.0E-7</td></tr><tr><td>Num_of_Zones</td><td>16</td><td>16</td></tr><tr><td>Burst_Size</td><td>32</td><td>32</td></tr></table> <h2>SDRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DRAM_Speed_Mhz</td><td>DRAM_Speed_Mhz</td><td>50.0</td></tr><tr><td>DRAM_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Refresh_Period</td><td>16.0e-3</td><td>0.016</td></tr><tr><td>Refresh_Cycles</td><td>8</td><td>8</td></tr><tr><td>Refresh_Priority</td><td>8</td><td>8</td></tr></table> <h2>A8_R4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>ARM_Speed_MHz</td><td>200.0</td><td>200.0</td></tr><tr><td>ARM_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Start_Code_Address</td><td>32 /* Multiple of 32 */</td><td>32</td></tr><tr><td>Function_Size_Words</td><td>85</td><td>85</td></tr><tr><td>Cache_Width_Bytes</td><td>32</td><td>32</td></tr><tr><td>Prefetch_Bytes</td><td>Cache_Width_Bytes</td><td>32</td></tr><tr><td>Priority</td><td>1</td><td>1</td></tr></table>

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