AMD Infinity Switch

Designing a SoC or embedded system using the open-standard NoC. Slight variation as there are some additional channels and an optional Forwarding Table at the Router.

NoC_Demo_Web

Browsable image of the model.

  • To download OpenWebStart click on the links -
    Windows- Compatibility:Windows 10 or higher (*)
    macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
    Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
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  • To simulate, click on Launch button, open downloaded file and click Run on the Java Security Page.
NoC_Demo_Webmodel <h2>ResourceStatistics</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;Multi_Block_Stats&quot;</td><td>&quot;Multi_Block_Stats&quot;</td></tr><tr><td>Scheduler_Name_Array</td><td>{} /* list of all the Schedulers as strings in a array */</td><td>{}</td></tr><tr><td>_explanation</td><td>Results-&gt;Resource_Statistical_Report</td><td>Results-&gt;Resource_Statistical_Report</td></tr><tr><td>Smart_Res_Length</td><td>{3,3,3,3} /* Number of Queues in each Smart_Resource and match the order in </td><td>{3, 3, 3, 3}</td></tr><tr><td>Number_of_Samples</td><td>6</td><td>6</td></tr><tr><td>Smart_Res_Name_Array</td><td>{&quot;R_1_1_Data&quot;,&quot;R_1_2_Data&quot;,&quot;R_2_1_Data&quot;,&quot;R_2_2_Data&quot;}</td><td>{&quot;R_1_1_Data&quot;, &quot;R_1_2_Data&quot;, &quot;R_2_1_Data&quot;, &quot;R_2_2_Data&quot;}</td></tr><tr><td>Statistics</td><td>true  /* Reset is false and Statistics is true */ </td><td>true</td></tr><tr><td>SimTime</td><td>SimTime</td><td>1.0E-4</td></tr></table> <h2>RNF</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Frequency</td><td>50.0e6</td><td>5.0E7</td></tr><tr><td>Data_Bytes_low</td><td>32</td><td>32</td></tr><tr><td>Data_Bytes_high</td><td>128</td><td>128</td></tr><tr><td>Destination_Address</td><td>&quot;HNF_1&quot;</td><td>&quot;HNF_1&quot;</td></tr><tr><td>Source_Address</td><td>&quot;RNF_3&quot;</td><td>&quot;RNF_3&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Device_Threshold</td><td>100</td><td>100</td></tr><tr><td>TrafficRate</td><td>20.0 * 1.0/Frequency</td><td>4.0E-7</td></tr><tr><td>Address_Low</td><td>0</td><td>0</td></tr><tr><td>Address_High</td><td>1023</td><td>1023</td></tr><tr><td>Random_Address</td><td>true</td><td>true</td></tr><tr><td>Request_Priority</td><td>&quot;All&quot;</td><td>&quot;All&quot;</td></tr><tr><td>Array_Routing</td><td>false</td><td>false</td></tr></table> <h2>R_2_2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Ingress_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>VC_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>Router_Address</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>Router_Frequency</td><td>Router_Frequency</td><td>8.0E8</td></tr><tr><td>Node_Name</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Router_Coordinate</td><td>{2,2}</td><td>{2, 2}</td></tr><tr><td>Router_Queue_Length</td><td>6</td><td>6</td></tr></table> <h2>R_2_1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Ingress_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>VC_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>Router_Address</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>Router_Frequency</td><td>Router_Frequency</td><td>8.0E8</td></tr><tr><td>Node_Name</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Router_Coordinate</td><td>{2,1}</td><td>{2, 1}</td></tr><tr><td>Router_Queue_Length</td><td>6</td><td>6</td></tr></table> <h2>R_1_2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Ingress_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>VC_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>Router_Address</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>Router_Frequency</td><td>Router_Frequency</td><td>8.0E8</td></tr><tr><td>Node_Name</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Router_Coordinate</td><td>{1,2}</td><td>{1, 2}</td></tr><tr><td>Router_Queue_Length</td><td>6</td><td>6</td></tr></table> <h2>HNI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Frequency</td><td>100.0e6</td><td>1.0E8</td></tr><tr><td>Source_Address</td><td>&quot;HNI_1&quot;</td><td>&quot;HNI_1&quot;</td></tr><tr><td>Device_Threshold</td><td>50</td><td>50</td></tr></table> <h2>RNI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Data_Bytes_low</td><td>32</td><td>32</td></tr><tr><td>Destination_Address</td><td>&quot;HNI_1&quot;</td><td>&quot;HNI_1&quot;</td></tr><tr><td>Source_Address</td><td>&quot;RNI_1&quot;</td><td>&quot;RNI_1&quot;</td></tr><tr><td>TrafficRate</td><td>10.0 * 1.0/Frequency</td><td>3.3333333333333E-8</td></tr><tr><td>Data_Bytes_high</td><td>64</td><td>64</td></tr><tr><td>Frequency</td><td>300.0e6</td><td>3.0E8</td></tr><tr><td>Array_Routing</td><td>false</td><td>false</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>AMBA_AXI</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AXI_Top&quot;</td><td>&quot;AXI_Top&quot;</td></tr><tr><td>AXI_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>AXI_Cycle_Time</td><td>1.0E-06 / AXI_Speed_Mhz</td><td>1.0E-9</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td><td>Interfaces and Buses-&gt;AHB-&gt;AXI_Bus</td></tr><tr><td>Bus_Width</td><td>8</td><td>8</td></tr><tr><td>Read_Threshold</td><td>2</td><td>2</td></tr><tr><td>Write_Threshold</td><td>2</td><td>2</td></tr><tr><td>Master_Request_Threshold</td><td>{2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2}  </td><td>{2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}</td></tr><tr><td>Number_Masters</td><td>16</td><td>16</td></tr><tr><td>Number_Slaves</td><td>8</td><td>8</td></tr><tr><td>Threshold_Trans_T_Bytes_F</td><td>false</td><td>false</td></tr><tr><td>Arbiter_FIX_1_RR_2_CUSTOM_3</td><td>1</td><td>1</td></tr><tr><td>Slave_Speeds_Mhz</td><td>{AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz,AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz, AXI_Speed_Mhz}</td><td>{1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0, 1000.0}</td></tr><tr><td>Extra_Cycles_for_RdReq_WrReq_RdData_WrData</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td><td>{0, 0, 0, 0, 0, 0, 0, 0}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;SDRAM&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;SDRAM&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr><tr><td>Master_First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Master_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Slave_Throttle_Enable</td><td>{false,false,false,false,false,false,false,false}  </td><td>{false, false, false, false, false, false, false, false}</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Fixed_Priority_Array</td><td>{{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16},{1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}}</td><td>{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}}</td></tr><tr><td>Slave_First_Word_Flag</td><td>true  /* Not Active in Default Slave */</td><td>true</td></tr><tr><td>Custom_Slave_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Ports_to_Plot</td><td>{0,0} /* master n, slave m, 0 disables */</td><td>{0, 0}</td></tr></table> <h2>Buffer Stats</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Stats</td><td>true</td><td>true</td></tr></table> <h2>Delay7</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_2_1_to_R_2_2&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>false</td><td>false</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>0</td><td>0</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay6</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_2_2_to_R_2_1&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_1_2_to_R_2_2&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>false</td><td>false</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>90</td><td>90</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_2_2&quot;</td><td>&quot;R_2_2&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_2_2_to_R_1_2&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>270</td><td>270</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_1_1_to_R_2_1&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>false</td><td>false</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>90</td><td>90</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_1_1_to_R_1_2&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>false</td><td>false</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>0</td><td>0</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Delay9</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_2_1&quot;</td><td>&quot;R_2_1&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_2_1_to_R_1_1&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>270</td><td>270</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>End_To_End Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Memory Stats</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>true</td><td>true</td></tr><tr><td>fileName</td><td>Memory_Stats.txt</td><td>&quot;Memory_Stats.txt&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Router Stats</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>true</td><td>true</td></tr><tr><td>fileName</td><td>Router_Stats.txt</td><td>&quot;Router_Stats.txt&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Delay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Start_Device</td><td>&quot;R_1_2&quot;</td><td>&quot;R_1_2&quot;</td></tr><tr><td>End_Device</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>Delay_Name</td><td>Start_Device + &quot;_to_&quot; + End_Device</td><td>&quot;R_1_2_to_R_1_1&quot;</td></tr><tr><td>Wire_Length</td><td>1e-8</td><td>1.0E-8</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr><tr><td>Clock_Speed</td><td>200e6</td><td>2.0E8</td></tr><tr><td>Delay_Cycles</td><td>1</td><td>1</td></tr></table> <h2>Database4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;Forwarding_Table&quot;</td><td>&quot;Forwarding_Table&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Source   A_Destination   A_Path;\\n&quot;HNF_1&quot;                 &quot;RNF_1&quot;            {&quot;R_2_2&quot;,&quot;R_2_1&quot;,&quot;R_1_1&quot;};\\n&quot;HNF_1&quot;                 &quot;RNF_3&quot;            {&quot;R_2_2&quot;,&quot;R_1_2&quot;};  \\n&quot;HNF_1&quot;                 &quot;RNF_5&quot;            {&quot;R_2_2&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_1&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_1&quot;\t                &quot;HNF_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;,&quot;R_2_2&quot;};\\n&quot;RNI_1&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_3&quot;\t                &quot;HNF_1&quot;            {&quot;R_1_2&quot;,&quot;R_2_2&quot;};\\n&quot;RNF_3&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_2&quot;,&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_5&quot;\t                &quot;HNF_1&quot;            {&quot;R_2_1&quot;,&quot;R_2_2&quot;};\\n</td><td>A_Source   A_Destination   A_Path;\\n&quot;HNF_1&quot;                 &quot;RNF_1&quot;            {&quot;R_2_2&quot;,&quot;R_2_1&quot;,&quot;R_1_1&quot;};\\n&quot;HNF_1&quot;                 &quot;RNF_3&quot;            {&quot;R_2_2&quot;,&quot;R_1_2&quot;};  \\n&quot;HNF_1&quot;                 &quot;RNF_5&quot;            {&quot;R_2_2&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_1&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_1&quot;\t                &quot;HNF_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;,&quot;R_2_2&quot;};\\n&quot;RNI_1&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_3&quot;\t                &quot;HNF_1&quot;            {&quot;R_1_2&quot;,&quot;R_2_2&quot;};\\n&quot;RNF_3&quot;\t                &quot;HNI_1&quot;            {&quot;R_1_2&quot;,&quot;R_1_1&quot;,&quot;R_2_1&quot;};\\n&quot;RNF_5&quot;\t                &quot;HNF_1&quot;            {&quot;R_2_1&quot;,&quot;R_2_2&quot;};\\n</td></tr><tr><td>Input_Fields</td><td>&quot;A_Source,A_Destination&quot;</td><td>&quot;A_Source,A_Destination&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;A_Source,A_Destination&quot;</td><td>&quot;A_Source,A_Destination&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>HNF_1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Next_Device</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>Frequency</td><td>100.0e6</td><td>1.0E8</td></tr><tr><td>Flit_Size</td><td>64</td><td>64</td></tr><tr><td>Num_Queues</td><td>16</td><td>16</td></tr><tr><td>Source_Address</td><td>&quot;HNF_1&quot;</td><td>&quot;HNF_1&quot;</td></tr><tr><td>Device_Threshold</td><td>50</td><td>50</td></tr></table> <h2>R_1_1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Ingress_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>VC_Buffer_Size</td><td>10</td><td>10</td></tr><tr><td>Router_Address</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>Router_Frequency</td><td>Router_Frequency</td><td>8.0E8</td></tr><tr><td>Node_Name</td><td>&quot;R_1_1&quot;</td><td>&quot;R_1_1&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Router_Coordinate</td><td>{1,1}</td><td>{1, 1}</td></tr><tr><td>Router_Queue_Length</td><td>6</td><td>6</td></tr></table> <h2>RNF_1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Frequency</td><td>300.0e6</td><td>3.0E8</td></tr><tr><td>Data_Bytes_low</td><td>32</td><td>32</td></tr><tr><td>Data_Bytes_high</td><td>128</td><td>128</td></tr><tr><td>Destination_Address</td><td>&quot;HNF_1&quot;</td><td>&quot;HNF_1&quot;</td></tr><tr><td>Source_Address</td><td>&quot;RNF_1&quot;</td><td>&quot;RNF_1&quot;</td></tr><tr><td>VLAN_Q</td><td>4</td><td>4</td></tr><tr><td>Device_Threshold</td><td>100</td><td>100</td></tr><tr><td>TrafficRate</td><td>10.0 * 1.0/Frequency</td><td>3.3333333333333E-8</td></tr><tr><td>Address_Low</td><td>0</td><td>0</td></tr><tr><td>Address_High</td><td>1023</td><td>1023</td></tr><tr><td>Random_Address</td><td>true</td><td>true</td></tr><tr><td>Request_Priority</td><td>&quot;All&quot;</td><td>&quot;All&quot;</td></tr><tr><td>Array_Routing</td><td>false</td><td>false</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Source_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td><td>Source_Node    Destination_Node   Hop           Source_Port ; \\nProcessor_1    Cache_1            Port_1        bus_out2    ;\\nCache_1        Processor_1        Port_2        output      ;\\nCache_1        SDRAM_1            Port_2        output      ;\\nSDRAM_1        Cache_1            Port_4        output      ;\\nSDRAM_1        Processor_1        Port_4        output      ;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */</td><td>/* First row contains Column Names.                */</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;SDRAM_Utilization_Min, SDRAM_Utilization_Mean, SDRAM_Utilization_Max&quot;</td><td>&quot;SDRAM_Utilization_Min, SDRAM_Utilization_Mean, SDRAM_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>DRAM</td><td>DRAM</td></tr></table> <h2>Memory_Controller</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Controller_Name</td><td>&quot;LPDDR&quot;</td><td>&quot;LPDDR&quot;</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Controller_Speed_Mhz</td><td>500.0</td><td>500.0</td></tr><tr><td>Memory_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Bus_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Command_Buffer_Length</td><td>8</td><td>8</td></tr><tr><td>Commands_in_a_Row</td><td>8</td><td>8</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{3,7,8,17} /* tCL, tRCD, tRP, tRAS */</td><td>{3, 7, 8, 17}</td></tr><tr><td>Extra_Timing</td><td>{1,3,4,1,3,1,1,1,0} /* DQSS, tWTR, tRRD,tWR, tRL, tWL, tDQSCK, tRTP, tHWpre */</td><td>{1, 3, 4, 1, 3, 1, 1, 1, 0}</td></tr><tr><td>Burst_Length</td><td>4 /* 2, 4, 8 */</td><td>4</td></tr><tr><td>Memory_Column</td><td>{2,9}</td><td>{2, 9}</td></tr><tr><td>Memory_Row</td><td>{10,24}</td><td>{10, 24}</td></tr><tr><td>Memory_Bank</td><td>{0,1}</td><td>{0, 1}</td></tr><tr><td>Memory_Bank_Length</td><td>round(pow(2,(Memory_Bank(1) - Memory_Bank(0) + 1)))</td><td>4L</td></tr><tr><td>DRAM_Return_Cycles</td><td>0</td><td>0</td></tr><tr><td>First_Word_Flag</td><td>true</td><td>true</td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>1.0E-4</td></tr><tr><td>Custom_Arbiter_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Custom_Arbiter_Path</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td><td>Hardware_Modeling-&gt;Memory-&gt;Memory_Controller</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot;  /* Default */</td><td>&quot;none&quot;</td></tr></table> <h2>HW_DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>HW_DRAM_Speed_Mhz</td><td>500.0</td><td>500.0</td></tr><tr><td>Number_of_Banks</td><td>8</td><td>8</td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>1.0E-4</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td><td>Hardware_Modeling-&gt;Memory-&gt;HW_DRAM</td></tr><tr><td>Memory_Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Length</td><td>4 /* 2, 4, 8 */</td><td>4</td></tr><tr><td>DRAM_Type</td><td>&quot;LPDDR2_S2&quot; /* SDR, DDR, DDR2, LPDDR, LPDDR2_NV, LPDDR2_S2, LPDDR2_S4, LPDDR3, DDR3 */</td><td>&quot;LPDDR2_S2&quot;</td></tr><tr><td>Mfg_Suggest_Timing</td><td>{2,2,2,6} /* tCAS, tRCD, tRP, tRAS */</td><td>{2, 2, 2, 6}</td></tr><tr><td>Extra_Timing</td><td>{2,2,1,1,3,1,2,1,0,16} /* DQSS, tWTR, tRRD, tWR, tRL, tWL , tDQSCK, tRTP, tHWpre, tFAW */</td><td>{2, 2, 1, 1, 3, 1, 2, 1, 0, 16}</td></tr><tr><td>Fix_DQSS</td><td>true</td><td>true</td></tr><tr><td>Refresh_Rate_per_Bank_ms</td><td>64.0 /* 64.0 ms */</td><td>64.0</td></tr><tr><td>Refresh_Cycles_per_Bank</td><td>256 /* 256 cycles per bank */</td><td>256</td></tr><tr><td>Enable_External_Data</td><td>false</td><td>false</td></tr><tr><td>Address_Bit_Map</td><td>{{2,9},{10,24},{0,1}}  /* col, row, bank (min, max) Bit Position */</td><td>{{2, 9}, {10, 24}, {0, 1}}</td></tr><tr><td>Standard_Name</td><td>&quot;none&quot; /*reads DDR_Memory_Standards.txt */</td><td>&quot;none&quot;</td></tr><tr><td>Standard_File</td><td>VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt</td><td>&quot;VS/VisualSim/actor/arch/Memory/DDR_Memory_Standards.txt&quot;</td></tr><tr><td>Power_Manager_Name</td><td>&quot;none&quot;  /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Memory_Controller</td><td>&quot;none&quot;  /* Default */</td><td>&quot;none&quot;</td></tr><tr><td>Bank_at_a_Time</td><td>true  /* false=all */</td><td>true</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>CycleAccurateCache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_L3&quot;</td><td>&quot;Cache_L3&quot;</td></tr><tr><td>Cache_Size_KB</td><td>16</td><td>16</td></tr><tr><td>Cache_Speed_Mhz</td><td>1000.0</td><td>1000.0</td></tr><tr><td>Cache_Bytes_per_Word</td><td>8</td><td>8</td></tr><tr><td>Bus_Width_Bytes</td><td>16</td><td>16</td></tr><tr><td>Cache_Line_Words</td><td>8</td><td>8</td></tr><tr><td>Cache_N_Associativity</td><td>4  /* 0 (Full Associaitive,1(Direct),2,4,8,16,32 */</td><td>4</td></tr><tr><td>Cache_Replacement_Policy</td><td>&quot;Least_Recently_Used&quot;  /* Least_Recently_Used, Most_Recently_Used */</td><td>&quot;Least_Recently_Used&quot;</td></tr><tr><td>Cache_Write_Policy</td><td>&quot;Write_Back&quot;  /* Write_Back, Write_Through */</td><td>&quot;Write_Back&quot;</td></tr><tr><td>Cache_Prefetch_Lines</td><td>1  /* 0,1,2,3... */</td><td>1</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>Next_Higher_Memory_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>First_Word_Flag</td><td>false</td><td>false</td></tr><tr><td>Snooping_Flag</td><td>false</td><td>false</td></tr><tr><td>Read_File</td><td>&quot;none&quot;</td><td>&quot;none&quot;</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td><td>ProcessorGenerator-&gt;CycleAccurateCache</td></tr><tr><td>Number_Statistics_Samples</td><td>1</td><td>1</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Next_Memory_Bus</td><td>true</td><td>true</td></tr></table> <h2>Database2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mac_ID     :: Mac_ID Address   Mbps       :: Data rate\\nSize_Bytes :: 1500             Start_Time :: 0.0    \\nStop_Time  :: 1.0E-03          Protocol   :: TCP_IP or UDP</td><td>Mac_ID     :: Mac_ID Address   Mbps       :: Data rate\\nSize_Bytes :: 1500             Start_Time :: 0.0    \\nStop_Time  :: 1.0E-03          Protocol   :: TCP_IP or UDP</td></tr><tr><td>Linking_Name</td><td>&quot;VLAN&quot;</td><td>&quot;VLAN&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>VLAN_ID  Bandwidth   \t;       \\n  1       200.0e6    \t; \\n  2       200.0e6 \t; \\n  3       200.0e6   \t; \\n  4       200.0e6   \t; \\n</td><td>VLAN_ID  Bandwidth   \t;       \\n  1       200.0e6    \t; \\n  2       200.0e6 \t; \\n  3       200.0e6   \t; \\n  4       200.0e6   \t; \\n</td></tr><tr><td>Input_Fields</td><td>&quot;VLAN_ID&quot;</td><td>&quot;VLAN_ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;VLAN_ID&quot;</td><td>&quot;VLAN_ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match_all&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match_all&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Router_C_Address -&gt; Current Router Address\\nRouter_D_Address -&gt; Destination Router Address\\n</td><td>Router_C_Address -&gt; Current Router Address\\nRouter_D_Address -&gt; Destination Router Address\\n</td></tr><tr><td>Linking_Name</td><td>&quot;AddressDecoder&quot;</td><td>&quot;AddressDecoder&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>Router_C_Address   A_Destination   Router_Hop_Address;\\n&quot;R_1_1&quot;                 &quot;RNF_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_1_1&quot;                 &quot;RNI_1&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_1_1&quot;                 &quot;R_1_2&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_1_1&quot;                 &quot;R_2_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_1&quot;                 &quot;HNF_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_1&quot;                 &quot;HNI_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_2&quot;                 &quot;RNF_3&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_1_2&quot;                 &quot;RNF_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_1_2&quot;                 &quot;RNF_4&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_1_2&quot;                 &quot;R_1_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_1_2&quot;                 &quot;R_2_2&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_2&quot;                 &quot;HNI_1&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_1_2&quot;                 &quot;HNF_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_2_1&quot;\t                &quot;HNI_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_1&quot;\t                &quot;RNF_6&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_2_1&quot;\t                &quot;R_1_1&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_1&quot;\t                &quot;R_2_2&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_2_1&quot;\t                &quot;HNF_1&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_2_1&quot;\t                &quot;HNI_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_1&quot;\t                &quot;RNF_1&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_2&quot;\t                &quot;HNF_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_2&quot;\t                &quot;R_1_2&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_2&quot;\t                &quot;R_2_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_2_2&quot;\t                &quot;RNF_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_2_2&quot;\t                &quot;RNF_3&quot;            &quot;0x00002&quot;;   /*North*/</td><td>Router_C_Address   A_Destination   Router_Hop_Address;\\n&quot;R_1_1&quot;                 &quot;RNF_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_1_1&quot;                 &quot;RNI_1&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_1_1&quot;                 &quot;R_1_2&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_1_1&quot;                 &quot;R_2_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_1&quot;                 &quot;HNF_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_1&quot;                 &quot;HNI_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_2&quot;                 &quot;RNF_3&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_1_2&quot;                 &quot;RNF_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_1_2&quot;                 &quot;RNF_4&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_1_2&quot;                 &quot;R_1_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_1_2&quot;                 &quot;R_2_2&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_1_2&quot;                 &quot;HNI_1&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_1_2&quot;                 &quot;HNF_1&quot;            &quot;0x00004&quot;;   /*South*/\\n&quot;R_2_1&quot;\t                &quot;HNI_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_1&quot;\t                &quot;RNF_6&quot;            &quot;0x00006&quot;;   /*Device2*/\\n&quot;R_2_1&quot;\t                &quot;R_1_1&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_1&quot;\t                &quot;R_2_2&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_2_1&quot;\t                &quot;HNF_1&quot;            &quot;0x00003&quot;;   /*East*/\\n&quot;R_2_1&quot;\t                &quot;HNI_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_1&quot;\t                &quot;RNF_1&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_2&quot;\t                &quot;HNF_1&quot;            &quot;0x00001&quot;;   /*Device*/\\n&quot;R_2_2&quot;\t                &quot;R_1_2&quot;            &quot;0x00002&quot;;   /*North*/\\n&quot;R_2_2&quot;\t                &quot;R_2_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_2_2&quot;\t                &quot;RNF_1&quot;            &quot;0x00005&quot;;   /*West*/\\n&quot;R_2_2&quot;\t                &quot;RNF_3&quot;            &quot;0x00002&quot;;   /*North*/</td></tr><tr><td>Input_Fields</td><td>&quot;Router_C_Address,A_Destination&quot;</td><td>&quot;Router_C_Address,A_Destination&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;Router_C_Address,A_Destination&quot;</td><td>&quot;Router_C_Address,A_Destination&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table>

Extends the AMD Infinity Switch with additional channels for Data And Acknowledge.

Network on Chip Architecture

A Network on Chip (NoC) is typically a communication subsystem on an IC. They are commonly used in conjunction with the cores within SoCs to bring out notable improvements to the entire system over conventional bus interconnections.

Diagram No.1 NoC Architecture

Routers are used between the Nodes(Cores) to transfer data and requests. The current design is based on the ARM Corelink Cache Coherent Network which is used as a cache coherency mechanism in a system with several IP Cores. The types of devices present in the NoC are Request Nodes, Home Nodes, and Routers. There are two types of request and home nodes which are modelled in this project. RNF (Fully Coherent Request Node), RNI (I/O Request Node), HNF (Fully Coherent Home Node), and HNI (I/O Home Node). The RNFs are fully coherent master devices that represent the processor cores in the NoC. The HNFs act as coherent region of the Memory which take in requests from the RNFs, handle snoops, and communicate with the cache and DRAM, and handles responses and acknowledgements. The RNIs and HNIs represent the I/O devices where the RNI sends data to the HNI, which acts as a sink.

RNF

The RNFs are typically traffic sources that produce and pass on requests to the Home Nodes. Expression List blocks and Script blocks are used to add fields to the data structure. Some of these fields are Request Type, Request Size, Data Size, Memory Address, Priority, Source and Destination addresses. Currently four Request Types are being used which are, ReadNoSnp, ReadSnp, WriteNoSnp, and WriteSnp. Each request types are handled differently by the Home Node. The input port of the RNF receives responses, acknowledgements, and data from the home nodes.

HNF

HNFs act as smart memory interface blocks within the NoC. They receive and processes the requests received from the Request nodes. The HNF stores all the incoming requests in 16 queues depending on their priorities. It then uses a popping mechanism based on an algorithm that uses wait times, priority levels, and round robin arbitration within priority groups to pop the right queue at the right time. The HNF also updates the database when a new request comes in to facilitate snoops. When the requests come out of the queue, a script is used to make the Home Node react differently to each type of requests.

Request Types Supported

(i) ReadNoSnp – Read without Snoop

HNF sends a response back to the Request Node. Sends a read request for the corresponding address to the Cache. The Cache sends data back to the HNF which in turn is sent to the Request Node.

(ii) ReadSnp – Read with Snoop

HNF sends a response back to the Request Node. It checks the database to see if any other Request Node has written the data at the same address before. If already written, it sends a data snoop request to the other RNF. The other RNF, after receiving the snoop request sends the data back to the HNF. Now the HNF forwards the data to the original RNF which requested the data. If the HNF did not find a previous write on the same address by other RNFs, it sends a read request to the Cache and sends the data back to the RNF.

(iii) WriteNoSnp – Write without Snoop

HNF sends a response back to the Request Node. The RNF, after receiving the response from the HNF, sends the data to be written. The HNF gets the data and passes it on to the Cache. After writing the Cache sends a response to the HNF, which in turn will send an Acknowledgment back to the RNF.

(iv) WriteSnp – Write with Snoop

HNF sends a response back to the Request Node. The HNF checks the database to see if any previous reads have occurred on the same address by other request nodes. If Yes, the HNF sends notifications to the corresponding RNFs. The RNF, after receiving the response for data from the HNF, sends the data to be written. The HNF gets the data and passes it on to the Cache. After writing the Cache sends a response to the HNF, which in turn will send an Acknowledgment back to the RNF.

Details on the Support Flows

ReadNoSnp --> Read No Snoop

RNF_1 sends Request to HNF_1 --> HNF_1 sends Response to RNF_1 --> HNF_1 reads Local Cache --> HNF sends Data to RNF_1

ReadSnp --> Read Snoop

RNF_1 sends Request to HNF_1 --> HNF_1 sends Response to RNF_1 --> HNF_1 reads Database --> If Data already written by RNF_2 ? ? --> Yes = HNF sends Data Request to RNF_2
--> RNF_2 sends Data to HNF_1
--> HNF_1 sends Data to RNF_1
? --> No = HNF reads Cache --> HNF sends Data to RNF

WriteNoSnp --> Write No Snoop

RNF_1 sends Request to HNF_1 --> HNF_1 sends Response to RNF_1 -> RNF_1 sends Data to HNF --> HNF_1 writes Data to Cache--> HNF_1 sends Ack to RNF_1 after writing

WriteSnp --> Write Snoop

RNF_1 sends Request to HNF_1 --> HNF_1 sends Response to RNF_1 --> HNF_1 reads Database --> If Data already read by RNF_2 ?
? --> Yes = HNF_1 Informs RNF_2

-->RNF_1 sends Data --> HNF_1 writes Data to Cache

--> HNF_1 sends Acknowledgement to RNF_1 after writing

RNI

I/O request nodes are simple traffic generators that produce data packets to send them to a I/O Home Node.

HNI

I/O home nodes are sinks where the data received from the RNIs and RNFs are sent through the I/O device.

Routers

Router blocks within the SoC guide the incoming requests and data to the right path by reading the destination field of the packets. The current design of the routers support two types of routing methods.

(i) Incoming packets possess the path from source to destination

(ii) Incoming packets possess the destination address alone

The router contains a crossbar which acts as the primary delay for the coming through. The crossbar has 4 Server blocks in total where each of them pass a different request type and data with a user defined delay.

The router also supports 2 devices at a time, where the device can be a home node or a request node. The routers also use the databases “Routing Table” and “Forwarding Table” to find the destination of the packets. A delay block is added to the wires between two routers to account for the overall wire delay.

Routing and Forwarding Table

Router_C_AddressA_Destination Router_Hop_Address;

"R_1_1" "RNF_1" "0x00001"; /*Device*/

"R_1_1" "RNI_1" "0x00006"; /*Device2*/

"R_1_1" "R_1_2" "0x00003"; /*East*/

"R_1_1" "R_2_1" "0x00004"; /*South*/

"R_1_1" "HNF_1" "0x00004"; /*South*/

"R_1_1" "HNI_1" "0x00004"; /*South*/

"R_1_2" "RNF_3" "0x00001"; /*Device*/

"R_1_2" "RNF_1" "0x00005"; /*West*/

"R_1_2" "RNF_4" "0x00006"; /*Device2*/

"R_1_2" "R_1_1" "0x00005"; /*West*/

"R_1_2" "R_2_2" "0x00004"; /*South*/

"R_1_2" "HNI_1" "0x00003"; /*East*/

"R_1_2" "HNF_1" "0x00004"; /*South*/

"R_2_1" "HNI_1" "0x00001"; /*Device*/

"R_2_1" "RNF_6" "0x00006"; /*Device2*/

"R_2_1" "R_1_1" "0x00002"; /*North*/

"R_2_1" "R_2_2" "0x00003"; /*East*/

"R_2_1" "HNF_1" "0x00003"; /*East*/

"R_2_1" "HNI_1" "0x00001"; /*Device*/

"R_2_1" "RNF_1" "0x00002"; /*North*/

"R_2_2" "HNF_1" "0x00001"; /*Device*/

"R_2_2" "R_1_2" "0x00002"; /*North*/

"R_2_2" "R_2_1" "0x00005"; /*West*/

"R_2_2" "RNF_1" "0x00005"; /*West*/

"R_2_2" "RNF_3" "0x00002"; /*North*/

Constructing SoC using NoC, AXI, Memory and IO library

VisualSim AMBA Corelink CMN600 library enables architects to explore the topology of the SoC using the CMN600 as the NoC. The library block supports devices, connectivity between routers, flits, fragmentation-assembly, virtual LAN, routing, snoop and separate channels for request, response, data and acknowledge.

Overview

The library consists of the following blocks:

  1. RN-F- Request Node- F
  2. RN-I- Request Node- Interface
  3. Router
  4. HN-F- Home Node- F
  5. HN-I- Home Node- Interface

Apart from this there are configuration blocks

Database:

  1. Home Node Database
  2. Forwarding Table- table is required but not used if Array_Routing is disabled
  3. Address Decode- used if Array_Routing is disabled. This is the default mechanism where the next hop is determined at each Router.
  4. VLAN- Required database but the model can restrict to one VLAN.

Support blocks:

  1. Digital Simulation- Must enter the simulation end time
  2. Architecture_Setup- to support the routing for the memory, cache and AXI bus
  3. Variable- Needed for internal setup
  4. Resource_Statistics- required block to generate the statistics for the Router. The name to be entered is the Router name.
  5. BufferStats- plots the buffer for all the ports of all the Routers.

Router configuration

To view the documentation for each block, right-click on the block and select Get Documentation.

To assemble the model

  1. Use the demo model as the application template
  2. Add additional instances of blocks from this model to assemble the topology of Routers.
  3. Either connect the wires directly between Router ports or add extra delays.
  4. Add the RN-F, RN-I, HN-F and HN-I in the right location
  5. Configure the parameters for blocks
  6. Configure the Database blocks for the routing at each Router. All done in a single Database.
  7. Add any cache and memory controller blocks.