MicroProcessor

Modeling the details of a 4-stage pipeline

Processor Generator

Comp_Model06d

Browsable image of the model.

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Comp_Model06dmodel <h2>PowerTable2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td><td>This is the Excel spreadsheet import. The power \\ninformation is maintained here.</td></tr><tr><td>Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Manager_Setup</td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n \\n--------Device Name------- ---------Power States------ -----Operating States------ -----------State Transitions--------- --Speed-- --Exist-- */\\n Architecture_Block Standby Active Wait Idle Existing OffState OnState t_OnOff Mhz Volts ; \\nMyPipeline_Power 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_I1_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_D1_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_L2_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_ALU 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bus 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bus2 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_DRAM 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Disk 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_XBar 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bridge 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; </td><td>/* Power_Table. First row contains Column Names, expressions valid for entries except Device Name. \\n \\n--------Device Name------- ---------Power States------ -----Operating States------ -----------State Transitions--------- --Speed-- --Exist-- */\\n Architecture_Block Standby Active Wait Idle Existing OffState OnState t_OnOff Mhz Volts ; \\nMyPipeline_Power 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_I1_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_D1_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_L2_Cache 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_ALU 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bus 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bus2 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_DRAM 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Disk 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_XBar 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; \\nScheduler_Bridge 70.0 350.0 0.0 0.0 Standby Standby Active 0.0 1000.0 1.0 ; </td></tr><tr><td>Async_State_Change</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n \\n--------Device Name------- ------------Time State--------- */\\n Architecture_Block State Time_or_Express Next ; \\n</td><td>/* Async_State_Change. First row contains Column Names, expressions valid for entries except Device Name. \\n \\n--------Device Name------- ------------Time State--------- */\\n Architecture_Block State Time_or_Express Next ; \\n</td></tr><tr><td>Expression_List</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- ------------------------------------Expression----------------------------------------------------------------------- */\\n Name Value ; \\n</td><td>/* First row contains Column Names. \\n \\n---------Reference-------- ------------------------------------Expression----------------------------------------------------------------------- */\\n Name Value ; \\n</td></tr><tr><td>Battery_Units</td><td>Milli_Watts</td><td>Milli_Watts</td></tr><tr><td>State_Plot_Enable</td><td>false</td><td>false</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&quot;Task_Completed&quot;</td><td>&quot;Task_Completed&quot;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>Bridge</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Bridge&quot;</td><td>&quot;Bridge&quot;</td></tr><tr><td>Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr></table> <h2>Disk</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;Disk&quot;</td><td>&quot;Disk&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr></table> <h2>Crossbar</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;XBar&quot;</td><td>&quot;XBar&quot;</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>DRAM_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr><tr><td>Cache_Name</td><td>&quot;I1_Cache&quot;</td><td>&quot;I1_Cache&quot;</td></tr><tr><td>Cache_Name2</td><td>&quot;D1_Cache&quot;</td><td>&quot;D1_Cache&quot;</td></tr></table> <h2>L2_Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>L2_Name</td><td>&quot;L2_Cache&quot;</td><td>&quot;L2_Cache&quot;</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr><tr><td>Hit_Ratio</td><td>0.95</td><td>0.95</td></tr><tr><td>Cache_Line_Words</td><td>Cache_Line_Words</td><td>16</td></tr><tr><td>Cache_Name</td><td>&quot;I1_Cache&quot;</td><td>&quot;I1_Cache&quot;</td></tr><tr><td>Cache_Name2</td><td>&quot;D1_Cache&quot;</td><td>&quot;D1_Cache&quot;</td></tr></table> <h2>L1_Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Cache_Name</td><td>&quot;I1_Cache&quot;</td><td>&quot;I1_Cache&quot;</td></tr><tr><td>Cache_Line_Words</td><td>Cache_Line_Words</td><td>16</td></tr><tr><td>Cache_Name2</td><td>&quot;D1_Cache&quot;</td><td>&quot;D1_Cache&quot;</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr><tr><td>Hit_Ratio</td><td>Cache_Hit_Ratio</td><td>0.95</td></tr><tr><td>Register_Hit_Ratio</td><td>0.90</td><td>0.9</td></tr><tr><td>Bus_Name</td><td>&quot;Bus&quot;</td><td>&quot;Bus&quot;</td></tr></table> <h2>Instant_Average_Power</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>Inst,Avg</td><td>Inst,Avg</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Shared_Resources</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Clock_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>L1_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>L2_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Bus_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>DRAM_Speed_Mhz</td><td>250.0</td><td>250.0</td></tr><tr><td>Disk_Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr></table> <h2>SW_Task</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;My_Task&quot;</td><td>&quot;My_Task&quot;</td></tr><tr><td>Instruction_Width_Bytes</td><td>Instruction_Width_Bytes</td><td>8</td></tr><tr><td>SimTime</td><td>SimTime</td><td>3.0E-5</td></tr><tr><td>Instruction_Rate</td><td>30.0E-06</td><td>3.0E-5</td></tr></table> <h2>Execution Unit</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Block_Name</td><td>&quot;ALU&quot;</td><td>&quot;ALU&quot;</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Width_Bytes</td><td>Interface_Width_Bytes</td><td>8</td></tr><tr><td>Register_Hit_Ratio</td><td>0.90</td><td>0.9</td></tr></table> <h2>VariableList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template \\nName Type Value */\\nI1_Cache_Words global Cache_Line_Words ; /* I1 Cache Words */\\nD1_Cache_Words global Cache_Line_Words ; /* D1 Cache Words */\\n</td><td>/* Memory Initialize Template \\nName Type Value */\\nI1_Cache_Words global Cache_Line_Words ; /* I1 Cache Words */\\nD1_Cache_Words global Cache_Line_Words ; /* D1 Cache Words */\\n</td></tr></table> <h2>Pipeline_All_Ports</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Sim_Time</td><td>SimTime</td><td>3.0E-5</td></tr><tr><td>Context_Switch_Cycles</td><td>1</td><td>1</td></tr><tr><td>DEBUG</td><td>false</td><td>false</td></tr><tr><td>Block_Name</td><td>&quot;MyPipeline&quot;</td><td>&quot;MyPipeline&quot;</td></tr><tr><td>Speed_Mhz</td><td>Processor_Speed_Mhz</td><td>1000.0</td></tr><tr><td>Power_Manager_Name</td><td>&quot;Manager_1&quot;</td><td>&quot;Manager_1&quot;</td></tr><tr><td>Number_of_Instructions</td><td>1000</td><td>1000</td></tr></table>

This Model illustrates a single core processor using a SW_Task, 4x_Pipeline, Registers, I_Cache, D_Cache, L2_Cache, Execution_Unit, XBar and DRAM. Bridge and Disk not used.