ARM Processor Family

Cortex M0 Microcontroller
Coming Soon
Cortex M3 Microcontroller
Using the standard M3 library product to construct a SoC controller for an IoT application
Cortex M4 Microcontrollers
Using the standard M4 library product to construct a SoC controller for an IoT application
A7
Dual ARM A7 executing AES code. Code was generated from the ARM Emulator
A8
Single ARM A8 Cortex implements an AES code. Includes power analysis, throughput, pipeline utilization and task latency
A9
Dual ARM Cortex A9 with a PCI interface sending traffic
A53
Modeling tasks on the A53 including loading and storing using a DMA
A72
Coming Soon
A76
Coming Soon
R4
Used for a encryption algorithm where the packet is decrypted and the data is filtered using a TI DSP C64x

ARM_Cortex_A53

Below is a browsable image of the model.

To download OpenWebStart click on the links -
Windows- Compatibility:Windows 10 or higher (*)
macOS - Compatibility:macOS 10.15 (Catalina) or higher (*)
Linux - Compatibility:Ubuntu 18.04 LTS or higher (*)
For an executable version,
To view or save the MoML file for this model, click here.

http://support.microsoft.com/gp/howtoscript

ARM Cortex A53 Processor System

This model shows VisualSim's Cortex A53 implementation by simulating a network application task profile provided
by NpBench. As soon as the model opens click on the RUN button (Green) in the toolbar at the top. You will see a
bunch of windows opening. These windows show the results obtained from the simulation such as Task Latency,
Task Set Latency, Power Consumption, and Statistics of the components of the model.

For further exploration of the model:
1) Double-Click on any block to get the specifications and parameters used for the block.
2)Some blocks, called hierarchical blocks, contain components within them. To see the working of a hierarchical block,
Right-Click on the block and select "Open Block". The hierarchical blocks present in this model are "Task Generator" and "Plots"

---------------------------------------Cortex A53 Model---------------------------------------

The Task Generator Hierarchical Block contains a traffic block, expression lists and a queue to simulate a set of 10 tasks in order.
The task profile is based on NpBench: A Network Processor benchmark tool. Each Task contains a random selection of instructions
based on the percentage of the kind of instruction defined in the task profile. The task generator links to an instuction mix table
which contains all details relating to the input tasks.

The simulated tasks are given to the Processor Block. Here, all the instructions are executed according to the details filled in the
"ARMv8_Instruction_Set" Block and the pipeline specified within the Processor block. All the executed instructions come out
of the processor through the output port of the block and the data structures from this port are used for plotting results.

The Processor is also connected to an external Cache and DRAM via a bus. These are memory blocks were the processor gets
data from when a miss occurs within internal cache. It also has DMA connected, which will give the processor the power to
access the DRAM directly.