Integrated_DSP_ARM_Platform_wout_DMA

Dual_ARM_7model <h2>DMA_Controller3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;PCI_DMA&quot;</td><td>&quot;PCI_DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase_2&quot;</td><td>&quot;DMADatabase_2&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>None</td><td>&quot;None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>16</td><td>&quot;16&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>128</td><td>128</td></tr><tr><td>DMA_to_Device_Mode</td><td>Custom</td><td>Custom</td></tr></table> <h2>Bus_Port6</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_1&quot;</td><td>&quot;AHB_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_11&quot;</td><td>&quot;Port_11&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_12&quot;</td><td>&quot;Port_12&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>PCI_Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>inter_time</td><td>500.0/33.0e6</td><td>1.5151515151515E-5</td></tr></table> <h2>Ethernet_traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>inter_time</td><td>500.0/100.0e6</td><td>5.0E-6</td></tr></table> <h2>DMA_Controller</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;Ethernet_DMA&quot;</td><td>&quot;Ethernet_DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase_1&quot;</td><td>&quot;DMADatabase_1&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>1</td><td>&quot;1&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>None</td><td>&quot;None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>16</td><td>&quot;16&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>&quot;100.0&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr></table> <h2>Bus_Port5</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_2&quot;</td><td>&quot;AHB_2&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_9&quot;</td><td>&quot;Port_9&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_10&quot;</td><td>&quot;Port_10&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>ARM7_2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;ARM7_2&quot;</td><td>&quot;ARM7_2&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM7_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed_Mhz\\nContext_Switch_Cycles: 200 /* switch between internal pipeline tasks */\\nInstruction_Queue_Length: 3 /* Can be varied */\\nNumber_of_Pipeline_Stages: 3 /* 3 Stages */\\nNumber_of_INT_Execution_Units: 1 /* 1 INT EU */\\nNumber_of_FP_Execution_Units: 0 /* 0 FP EU */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=I_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\nD_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=D_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM7_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed_Mhz\\nContext_Switch_Cycles: 200 /* switch between internal pipeline tasks */\\nInstruction_Queue_Length: 3 /* Can be varied */\\nNumber_of_Pipeline_Stages: 3 /* 3 Stages */\\nNumber_of_INT_Execution_Units: 1 /* 1 INT EU */\\nNumber_of_FP_Execution_Units: 0 /* 0 FP EU */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=I_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\nD_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=D_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\n</td></tr><tr><td>Pipeline_Stages</td><td>/* Pipeline stages in ARM7 */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_EXECUTE I_1 wait none ; /* Decode */\\n2_EXECUTE ARM7 exec none ; /* Execute ARM instr */ \\n3_MEMORY ARM7 wait none ; /* Wait for ARM instr */\\n3_MEMORY D_1 write none ; /* Write back */</td><td>/* Pipeline stages in ARM7 */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_EXECUTE I_1 wait none ; /* Decode */\\n2_EXECUTE ARM7 exec none ; /* Execute ARM instr */ \\n3_MEMORY ARM7 wait none ; /* Wait for ARM instr */\\n3_MEMORY D_1 write none ; /* Write back */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table> <h2>Bus_Controller2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_2&quot;</td><td>&quot;AHB_2&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>33.0</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>100</td><td>100</td></tr><tr><td>Control_Expression</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Data_Expression</td><td>&quot;String&quot;</td><td>&quot;String&quot;</td></tr></table> <h2>Bus_Port4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_2&quot;</td><td>&quot;AHB_2&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_7&quot;</td><td>&quot;Port_7&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_8&quot;</td><td>&quot;Port_8&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>Cache</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_L2&quot;</td><td>&quot;Cache_L2&quot;</td></tr><tr><td>Miss_Memory_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>Cache_Speed_Mhz</td><td>Cache_Speed_Mhz</td><td>66.0</td></tr><tr><td>Cache_Size_KBytes</td><td>Cache_Size_KB</td><td>32.0</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Words_per_Cache_Line</td><td>16</td><td>16</td></tr><tr><td>FIFO_Buffers</td><td>16</td><td>16</td></tr><tr><td>Cache_Address</td><td>&quot;101010&quot;</td><td>&quot;101010&quot;</td></tr><tr><td>Cache_Hit_Expression</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td><td>&quot;rand(0.0,1.0) &lt;= 0.95&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr></table> <h2>Bus_Port2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_1&quot;</td><td>&quot;AHB_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_3&quot;</td><td>&quot;Port_3&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_4&quot;</td><td>&quot;Port_4&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>Bus_Port</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_1&quot;</td><td>&quot;AHB_1&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_1&quot;</td><td>&quot;Port_1&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_2&quot;</td><td>&quot;Port_2&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>Bus_Controller</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_1&quot;</td><td>&quot;AHB_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>Bus_Speed_Mhz</td><td>33.0</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Burst_Size_Bytes</td><td>100</td><td>100</td></tr><tr><td>Control_Expression</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Data_Expression</td><td>&quot;String&quot;</td><td>&quot;String&quot;</td></tr></table> <h2>Bus_Port3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_2&quot;</td><td>&quot;AHB_2&quot;</td></tr><tr><td>Port_Name_1</td><td>&quot;Port_5&quot;</td><td>&quot;Port_5&quot;</td></tr><tr><td>Port_Name_2</td><td>&quot;Port_6&quot;</td><td>&quot;Port_6&quot;</td></tr><tr><td>Transaction_Buffers</td><td>16</td><td>16</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Port_Address_1</td><td>101</td><td>101</td></tr><tr><td>Port_Address_2</td><td>102</td><td>102</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;SDRAM_1&quot;</td><td>&quot;SDRAM_1&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>RAM_Speed_Mhz</td><td>33.0</td></tr><tr><td>Memory_Size_MBytes</td><td>RAM_Size_MB</td><td>8.0</td></tr><tr><td>Access_Time</td><td>RAM_Access_Time</td><td>&quot;Read 8.0,Prefetch 8.0,Refresh 8.0,Write 7.5&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>16</td><td>16</td></tr><tr><td>Memory_Address</td><td>&quot;101010&quot;</td><td>&quot;101010&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time&quot;</td><td>&quot;Cycle_Time&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>SDR</td><td>SDR</td></tr></table> <h2>ARM7_1</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mapping of ARM7 CPU architecture parameters to generic CPU\\n</td><td>Mapping of ARM7 CPU architecture parameters to generic CPU\\n</td></tr><tr><td>Architecture_Name</td><td>Arch_Name</td><td>&quot;Arch_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;ARM7_1&quot;</td><td>&quot;ARM7_1&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM7_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed_Mhz\\nContext_Switch_Cycles: 200 /* switch between internal pipeline tasks */\\nInstruction_Queue_Length: 3 /* Can be varied */\\nNumber_of_Pipeline_Stages: 3 /* 3 Stages */\\nNumber_of_INT_Execution_Units: 1 /* 1 INT EU */\\nNumber_of_FP_Execution_Units: 0 /* 0 FP EU */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=I_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\nD_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=D_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM7_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: Processor_Speed_Mhz\\nContext_Switch_Cycles: 200 /* switch between internal pipeline tasks */\\nInstruction_Queue_Length: 3 /* Can be varied */\\nNumber_of_Pipeline_Stages: 3 /* 3 Stages */\\nNumber_of_INT_Execution_Units: 1 /* 1 INT EU */\\nNumber_of_FP_Execution_Units: 0 /* 0 FP EU */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=I_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\nD_1: {Cache_Speed_Mhz=Processor_Speed_Mhz, Size_KBytes=D_Cache_KB, Words_per_Cache_Line=8, Cache_Miss_Name=Cache_L2} \\n</td></tr><tr><td>Pipeline_Stages</td><td>/* Pipeline stages in ARM7 */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_EXECUTE I_1 wait none ; /* Decode */\\n2_EXECUTE ARM7 exec none ; /* Execute ARM instr */ \\n3_MEMORY ARM7 wait none ; /* Wait for ARM instr */\\n3_MEMORY D_1 write none ; /* Write back */</td><td>/* Pipeline stages in ARM7 */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_EXECUTE I_1 wait none ; /* Decode */\\n2_EXECUTE ARM7 exec none ; /* Execute ARM instr */ \\n3_MEMORY ARM7 wait none ; /* Wait for ARM instr */\\n3_MEMORY D_1 write none ; /* Write back */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table>