Chiplet_UCIe_NOC_with_TG

Browsable image of the model.

Chiplet_UCIe_NOC_with_TGmodel <h2>UCIe_Debug</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr></table> <h2>Database</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mac_ID     :: Mac_ID Address   Mbps       :: Data rate<br/>Size_Bytes :: 1500             Start_Time :: 0.0    <br/>Stop_Time  :: 1.0E-03          Protocol   :: TCP_IP or UDP</td><td>Mac_ID     :: Mac_ID Address   Mbps       :: Data rate<br/>Size_Bytes :: 1500             Start_Time :: 0.0    <br/>Stop_Time  :: 1.0E-03          Protocol   :: TCP_IP or UDP</td></tr><tr><td>Linking_Name</td><td>&quot;VLAN&quot;</td><td>&quot;VLAN&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>VLAN_ID  Bandwidth   \t;       <br/>  1       200.0e6    \t; <br/>  2       200.0e6 \t; <br/>  3       200.0e6   \t; <br/>  4       200.0e6   \t; <br/></td><td>VLAN_ID  Bandwidth   \t;       <br/>  1       200.0e6    \t; <br/>  2       200.0e6 \t; <br/>  3       200.0e6   \t; <br/>  4       200.0e6   \t; <br/></td></tr><tr><td>Input_Fields</td><td>&quot;VLAN_ID&quot;</td><td>&quot;VLAN_ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;VLAN_ID&quot;</td><td>&quot;VLAN_ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match_all&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match_all&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Source_Node    Destination_Node   Hop           Source_Port ; <br/>Processor_1    Cache_1            Port_1        bus_out2    ;<br/>Cache_1        Processor_1        Port_2        output      ;<br/>Cache_1        SDRAM_1            Port_2        output      ;<br/>SDRAM_1        Cache_1            Port_4        output      ;<br/>SDRAM_1        Processor_1        Port_4        output      ;</td><td>Source_Node    Destination_Node   Hop           Source_Port ; <br/>Processor_1    Cache_1            Port_1        bus_out2    ;<br/>Cache_1        Processor_1        Port_2        output      ;<br/>Cache_1        SDRAM_1            Port_2        output      ;<br/>SDRAM_1        Cache_1            Port_4        output      ;<br/>SDRAM_1        Processor_1        Port_4        output      ;</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */</td><td>/* First row contains Column Names.                */</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Pct_Min, Processor_1_PROC_Utilization_Pct_Mean, Processor_1_PROC_Utilization_Pct_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Pct_Min, Processor_1_PROC_Utilization_Pct_Mean, Processor_1_PROC_Utilization_Pct_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */<br/>External_Field_Name          Internal_Field_Name   ; <br/>A_Address                    A_Address             ; <br/>A_Bytes                      A_Bytes               ; <br/>A_Data                       A_Data                ; <br/>A_IDX                        A_IDX                 ; <br/>A_Instruction                A_Instruction         ; <br/>A_Priority                   A_Priority            ; <br/>A_Source                     A_Source              ; <br/>A_Destination                A_Destination         ; <br/>A_Task_ID                    A_Task_ID             ; <br/>A_Time                       A_Time                ; <br/></td><td>/* First row contains Column Names.                */<br/>External_Field_Name          Internal_Field_Name   ; <br/>A_Address                    A_Address             ; <br/>A_Bytes                      A_Bytes               ; <br/>A_Data                       A_Data                ; <br/>A_IDX                        A_IDX                 ; <br/>A_Instruction                A_Instruction         ; <br/>A_Priority                   A_Priority            ; <br/>A_Source                     A_Source              ; <br/>A_Destination                A_Destination         ; <br/>A_Task_ID                    A_Task_ID             ; <br/>A_Time                       A_Time                ; <br/></td></tr></table> <h2>IO_Chiplet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>AI_Chiplet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>DSP_Chiplet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>GPU_Chiplet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>CPU_Chiplet</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>UCIE_Interconnect_with_NOC_Backbone</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>UCIe_Switch_Name</td><td>&quot;UCIe&quot;</td><td>&quot;UCIe&quot;</td></tr><tr><td>Ingress_Buf</td><td>1000</td><td>1000</td></tr><tr><td>VC_Buf</td><td>1000</td><td>1000</td></tr><tr><td>Frequency</td><td>100.0e6</td><td>1.0E8</td></tr><tr><td>Router_Frequency</td><td>800.0e6</td><td>8.0E8</td></tr><tr><td>Architecture_Setup_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Package_Type</td><td>Standard</td><td>&quot;Standard&quot;</td></tr><tr><td>Max_Link_Speed_GTps</td><td>{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32}</td><td>{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32}</td></tr><tr><td>Protocols_Per_Port</td><td>{{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;CXL_2_0&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;},{&quot;PCIe_Gen6&quot;}}</td><td>{{&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;CXL_2_0&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}, {&quot;PCIe_Gen6&quot;}}</td></tr><tr><td>Number_of_Modules</td><td>{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}</td><td>{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}</td></tr><tr><td>Retimer_Enable_Arr</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Max_Read_Req_Size_Bytes</td><td>4096</td><td>4096</td></tr><tr><td>Devices_Attached_to_Ports</td><td>{{&quot;Dev_1&quot;},{&quot;Dev_2&quot;},{&quot;Dev_3&quot;},{&quot;Dev_4&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;,&quot;IO_in1&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;},{&quot;Dev_13&quot;},{&quot;Dev_14&quot;},{&quot;Dev_15&quot;},{&quot;Dev_16&quot;},{&quot;Dev_17&quot;},{&quot;Dev_18&quot;}}</td><td>{{&quot;Dev_1&quot;}, {&quot;Dev_2&quot;}, {&quot;Dev_3&quot;}, {&quot;Dev_4&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;, &quot;IO_in1&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}, {&quot;Dev_13&quot;}, {&quot;Dev_14&quot;}, {&quot;Dev_15&quot;}, {&quot;Dev_16&quot;}, {&quot;Dev_17&quot;}, {&quot;Dev_18&quot;}}</td></tr><tr><td>Replay_Buffer_Size_Bytes</td><td>1024</td><td>1024</td></tr><tr><td>Retimer_Timeout</td><td>2.0e-3</td><td>0.002</td></tr><tr><td>Number_Of_Successive_Acks</td><td>3</td><td>3</td></tr><tr><td>Enable_Selective_Ack</td><td>true</td><td>true</td></tr><tr><td>Buffer_Size_Bytes</td><td>{4096,4096,4096} //Rx,Tx,Retimer_Rx</td><td>{4096, 4096, 4096}</td></tr><tr><td>Overhead_Cycles</td><td>0</td><td>0</td></tr><tr><td>BER</td><td>1.0e-27</td><td>1.0E-27</td></tr><tr><td>NumOfRetry</td><td>4</td><td>4</td></tr><tr><td>Timeout</td><td>6.0E-6</td><td>6.0E-6</td></tr><tr><td>Enable_Hello_Msg_Forwarding</td><td>true</td><td>true</td></tr><tr><td>Enable_Master_Flow_Control</td><td>false</td><td>false</td></tr><tr><td>Enable_Slave_Flow_Control</td><td>false</td><td>false</td></tr><tr><td>Enable_Debug</td><td>true</td><td>true</td></tr><tr><td>Flit_Size</td><td>64</td><td>64</td></tr><tr><td>Device_Threshold</td><td>5000</td><td>5000</td></tr></table>