Distributed Memory Architecture 12 Processor modules with 8 cores each conencted to a PCIe to 4 DRAM devices using a feature called Dynamic Instantiation
HPCSystemWithIDTSwitch
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This model was constructed for the paper published at the IEEE Aerospace Conference in 2016.
This model has 4 DSP boards that are inter-connected using a RapidIO backplane. The instructions are cached in the local memory while the data has to retrieved across the backbone form another board.