Large-Scale Servers

12 Processor modules with 8 cores each conencted to a PCIe to 4 DRAM devices using a feature called Dynamic Instantiation

PCIe_DMA

Browsable image of the model.

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PCIe_DMAmodel <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td><td>/* Template for List of Expressions.    \\n   Result_A = MyRegExpression_A_or_None \\n   Result_B = MyRegExpression_B_or_None \\n   Result_C = MyRegExpression_C_or_None \\n   Result_D = MyRegExpression_D_or_None \\n   End of Expressions                */ \\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>TNow -  input.TIME</td><td>&quot;TNow -  input.TIME&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>input.A_Task_Name = &quot;Display_Task&quot;\\ninput.A_Source = &quot;Trigger&quot;\\ninput.A_Instruction = (rand(0.0,1.0)&gt; 0.5)?{&quot;Store&quot;}:{&quot;Load&quot;}</td><td>input.A_Task_Name = &quot;Display_Task&quot;\\ninput.A_Source = &quot;Trigger&quot;\\ninput.A_Instruction = (rand(0.0,1.0)&gt; 0.5)?{&quot;Store&quot;}:{&quot;Load&quot;}</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>Traffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>Start_Time</td><td>1.0E-9</td><td>1.0E-9</td></tr><tr><td>Value_1</td><td>1.0E-6</td><td>1.0E-6</td></tr><tr><td>Value_2</td><td>2.0</td><td>2.0</td></tr><tr><td>Random_Seed</td><td>123457L</td><td>123457L</td></tr><tr><td>Time_Distribution</td><td>Fixed (Value_1)</td><td>Fixed (Value_1)</td></tr></table> <h2>Latency</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr><tr><td>_flipPortsVertical</td><td>true</td><td>true</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr><tr><td>_rotatePorts</td><td>180</td><td>180</td></tr></table> <h2>PCIe_Bus</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;PCIe_1&quot;</td><td>&quot;PCIe_1&quot;</td></tr><tr><td>Number_of_Lanes</td><td>16 /* Can be an array */</td><td>16</td></tr><tr><td>Slave_Buffer</td><td>512  /* Max Bytes @ Slave */</td><td>512</td></tr><tr><td>Master_Buffer</td><td>512  /* Max Bytes @ Master */</td><td>512</td></tr><tr><td>Sim_Time</td><td>1.0e-3</td><td>1.0E-3</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td><td>Interfaces and Buses-&gt;PCI-&gt;PCIe_Bus</td></tr><tr><td>Header_Bytes</td><td>16  /* 32 Bit Mode, includes CRC Bytes */</td><td>16</td></tr><tr><td>Number_of_Ports</td><td>{12, 12}  /* Master, Endpoint  Ports */</td><td>{12, 12}</td></tr><tr><td>BER</td><td>1.0E-11</td><td>1.0E-11</td></tr><tr><td>Max_Payload_Size</td><td>64  /* Write, Read Data */</td><td>64</td></tr><tr><td>Max_Payload_Req_Size</td><td>128  /* Read Requests */</td><td>128</td></tr><tr><td>PCIe_Gen_1</td><td>250.0  /* DO NOT MODIFY */</td><td>250.0</td></tr><tr><td>PCIe_Gen_2</td><td>500.0  /* DO NOT MODIFY */</td><td>500.0</td></tr><tr><td>PCIe_Gen_3</td><td>985.6  /* DO NOT MODIFY */</td><td>985.6</td></tr><tr><td>PCIe_Gen_4</td><td>1969.2  /* DO NOT MODIFY */</td><td>1969.2</td></tr><tr><td>PCIe_MBps</td><td>PCIe_Gen_2  /* Per Lane */</td><td>500.0</td></tr><tr><td>Read_to_Write_Ratio</td><td>0.5  /* 0.0 to 1.0 */</td><td>0.5</td></tr><tr><td>Devices_Attached_to_Slaves</td><td>{{&quot;DRAM&quot;},{&quot;Dev_2&quot;},{&quot;Dev_3&quot;},{&quot;Display&quot;},{&quot;Dev_5&quot;},{&quot;Dev_6&quot;},{&quot;Dev_7&quot;},{&quot;Dev_8&quot;},{&quot;Dev_9&quot;},{&quot;Dev_10&quot;},{&quot;Dev_11&quot;},{&quot;Dev_12&quot;}}</td><td>{{&quot;DRAM&quot;}, {&quot;Dev_2&quot;}, {&quot;Dev_3&quot;}, {&quot;Display&quot;}, {&quot;Dev_5&quot;}, {&quot;Dev_6&quot;}, {&quot;Dev_7&quot;}, {&quot;Dev_8&quot;}, {&quot;Dev_9&quot;}, {&quot;Dev_10&quot;}, {&quot;Dev_11&quot;}, {&quot;Dev_12&quot;}}</td></tr><tr><td>Root_Complex_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Endpoint_Flow_Control</td><td>{false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false}</td><td>{false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false}</td></tr><tr><td>Enable_Plots</td><td>true</td><td>true</td></tr><tr><td>Bit_64_Mode</td><td>true</td><td>true</td></tr></table> <h2>DeviceInterface</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Trigger&quot;</td><td>&quot;Trigger&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Fld_Name_or_String&quot;</td><td>&quot;Fld_Name_or_String&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr></table> <h2>DeviceInterface2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>IO_Name</td><td>&quot;Display&quot;</td><td>&quot;Display&quot;</td></tr><tr><td>IO_Destination</td><td>&quot;A_Source&quot;</td><td>&quot;A_Source&quot;</td></tr><tr><td>IO_Command</td><td>&quot;Write&quot;</td><td>&quot;Write&quot;</td></tr><tr><td>IO_Instruction</td><td>&quot;Fld_Name_or_String_or_None&quot;</td><td>&quot;Fld_Name_or_String_or_None&quot;</td></tr><tr><td>IO_Bytes</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Priority</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>IO_Address</td><td>&quot;Fld_Name_or_Integer&quot;</td><td>&quot;Fld_Name_or_Integer&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>Delay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Delay_Value</td><td>100.0e-9</td><td>&quot;100.0e-9&quot;</td></tr></table> <h2>VariableList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Memory_Init_Text</td><td>/* Memory Initialize Template          \\nName          Type          Value     */\\nSource        global         &quot;Processor&quot;       ;  /* Var */\\nAccess        global         &quot;Read&quot;            ;  /* DS2  */\\nCTRL_Time     global         100               ;</td><td>/* Memory Initialize Template          \\nName          Type          Value     */\\nSource        global         &quot;Processor&quot;       ;  /* Var */\\nAccess        global         &quot;Read&quot;            ;  /* DS2  */\\nCTRL_Time     global         100               ;</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;DRAM&quot;</td><td>&quot;DRAM&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>Bus_Speed</td><td>200.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 2.0, Write 3.0&quot;</td><td>&quot;Read 2.0, Write 3.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>16384</td><td>16384</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr><tr><td>Memory_Type</td><td>DDR</td><td>DDR</td></tr></table> <h2>DMADatabase</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td><td>*.xml, *.csv files abs or rel (./) path\\n  -- *.csv real columns set to number\\nInput_Fields == Lookup_Fields (num, type)\\nOutput_Expr: match, match_last, match_all\\n  -- match_all.field not allowed</td></tr><tr><td>Linking_Name</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>fileOrURL</td><td>&nbsp;</td><td>&quot;&quot;</td></tr><tr><td>Data_Structure_Text</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Command\tA_Bytes\tA_Priority\tA_Destination    \\nDisplay_Task    Load\t          0\t   Display\t       32\t        1          Read\t           200\t     0\t             DMA \\nDisplay_Task    Store\t          0\t   DRAM\t       \t       32\t        2          Write\t   150\t     0\t             DMA \\n\\n</td><td>A_Task_Name\tA_Instruction\tA_IDX\tA_Task_Source\tBurst_Word_Size\tA_Task_Address  A_Command\tA_Bytes\tA_Priority\tA_Destination    \\nDisplay_Task    Load\t          0\t   Display\t       32\t        1          Read\t           200\t     0\t             DMA \\nDisplay_Task    Store\t          0\t   DRAM\t       \t       32\t        2          Write\t   150\t     0\t             DMA \\n\\n</td></tr><tr><td>Input_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Lookup_Fields</td><td>&quot;ID&quot;</td><td>&quot;ID&quot;</td></tr><tr><td>Output_Expression</td><td>&quot;output = match&quot; /* FORMAT output = match.fieldb */</td><td>&quot;output = match&quot;</td></tr><tr><td>Mode</td><td>Read</td><td>Read</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>DMA_Controller_Name</td><td>&quot;DMA&quot;</td><td>&quot;DMA&quot;</td></tr><tr><td>Memory_Database_Reference</td><td>&quot;DMADatabase&quot;</td><td>&quot;DMADatabase&quot;</td></tr><tr><td>DMA_to_Device_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>DMA_to_Device_Address</td><td>DS_Fld_Name_or_Integer</td><td>&quot;DS_Fld_Name_or_Integer&quot;</td></tr><tr><td>Device_to_DMA_Cycles</td><td>RegEx_or_None</td><td>&quot;RegEx_or_None&quot;</td></tr><tr><td>Channel_FIFO_Buffers</td><td>10</td><td>&quot;10&quot;</td></tr><tr><td>Speed_Mhz</td><td>Bus_Speed</td><td>&quot;Bus_Speed&quot;</td></tr><tr><td>DMA_Channels</td><td>2</td><td>2</td></tr><tr><td>Width_Bytes</td><td>8</td><td>8</td></tr></table> <h2>ArchitectureSetup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td><td>/* First row contains Column Names.                */\\nExternal_Field_Name          Internal_Field_Name   ; \\nA_Address                    A_Address             ; \\nA_Bytes                      A_Bytes               ; \\nA_Data                       A_Data                ; \\nA_IDX                        A_IDX                 ; \\nA_Instruction                A_Instruction         ; \\nA_Priority                   A_Priority            ; \\nA_Source                     A_Source              ; \\nA_Destination                A_Destination         ; \\nA_Task_ID                    A_Task_ID             ; \\nA_Time                       A_Time                ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names.                */</td><td>/* First row contains Column Names.                */</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>None</td><td>None</td></tr></table>

This model uses the standard PCIe library in VisualSim to construct a system model. This model uses a DMA transaction that moves data from a Display to a DRAM. The tow lines of the Database block shows the sequence of operations.