ARM AMBA AHB Bus Matrix

Uses a AHB Bus Matrix to connect multiple processors to DRAM and Flash

AMBA Interface Family

AHB_MultiMaster_Fabric

Browsable image of the model.

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AHB_MultiMaster_Fabricmodel <h2>TextDisplay</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>rowsDisplayed</td><td>10</td><td>10</td></tr><tr><td>columnsDisplayed</td><td>40</td><td>40</td></tr><tr><td>suppressBlankLines</td><td>false</td><td>false</td></tr><tr><td>title</td><td>&nbsp;</td><td>&nbsp;</td></tr><tr><td>ViewText</td><td>true</td><td>true</td></tr><tr><td>saveText</td><td>false</td><td>false</td></tr><tr><td>fileName</td><td>Enter Filename to save text</td><td>&quot;Enter Filename to save text&quot;</td></tr><tr><td>Append_Time</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* No Expressions. */</td><td>/* No Expressions. */</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>(TNow - input.TIME)</td><td>&quot;(TNow - input.TIME)&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>ExpressionList</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Destination = &quot;ARM926&quot;\\ninput.A_Hop = &quot;ARM926&quot;\\ninput.TIME = TNow</td><td>/* Template to enter multiple RegEx lines*/\\ninput.A_Destination = &quot;ARM926&quot;\\ninput.A_Hop = &quot;ARM926&quot;\\ninput.TIME = TNow</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>true</td><td>&quot;true&quot;</td></tr></table> <h2>TriggeredTraffic</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Data_Structure_Name</td><td>&quot;Processor_DS&quot;</td><td>&quot;Processor_DS&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>true</td><td>true</td></tr></table> <h2>ExpressionList2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Expression_List</td><td>/* Template to enter multiple RegEx lines*/\\n \\n</td><td>/* Template to enter multiple RegEx lines*/\\n \\n</td></tr><tr><td>Output_Ports</td><td>output</td><td>&quot;output&quot;</td></tr><tr><td>Output_Values</td><td>input</td><td>&quot;input&quot;</td></tr><tr><td>Output_Conditions</td><td>input.containsRecordTokenLabel(&quot;TIME&quot;)</td><td>&quot;input.containsRecordTokenLabel(&quot;TIME&quot;)&quot;</td></tr><tr><td>_flipPortsHorizontal</td><td>false</td><td>false</td></tr></table> <h2>xTime_yData_Plotter</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>fillOnWrapup</td><td>true</td><td>true</td></tr><tr><td>legend</td><td>uP Task Latency, DMA Transfer</td><td>uP Task Latency, DMA Transfer</td></tr><tr><td>startingDataset</td><td>0</td><td>0</td></tr><tr><td>fileName</td><td>Enter Filename to save plot</td><td>&quot;Enter Filename to save plot&quot;</td></tr><tr><td>viewPlot</td><td>true</td><td>true</td></tr><tr><td>savePlot</td><td>false</td><td>false</td></tr></table> <h2>Flash</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Sequence_Read_Time</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Random_Read_Time</td><td>50.0e-6</td><td>5.0E-5</td></tr><tr><td>Write_Access</td><td>50.0e-9</td><td>5.0E-8</td></tr><tr><td>Arch_Setup</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Page_Size</td><td>2048</td><td>2048</td></tr><tr><td>Erase_Access</td><td>50.0</td><td>50.0</td></tr><tr><td>Read_Access_Time</td><td>50.0</td><td>50.0</td></tr><tr><td>Write_Access_Time</td><td>50.0</td><td>50.0</td></tr><tr><td>Erase_Access_Time</td><td>50.0</td><td>50.0</td></tr><tr><td>Flash_Name</td><td>&quot;Flash&quot;</td><td>&quot;Flash&quot;</td></tr><tr><td>Flash_CTRL_Name</td><td>&quot;Flash_Ctrl&quot;</td><td>&quot;Flash_Ctrl&quot;</td></tr></table> <h2>Switch</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Switch_Name</td><td>&quot;Switch&quot;</td><td>&quot;Switch&quot;</td></tr><tr><td>Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Blocking_Mode</td><td>false</td><td>false</td></tr><tr><td>_explanation</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Switch</td><td>Hardware_Modeling-&gt;Bus_Switch_Ctrl-&gt;Switch</td></tr><tr><td>Overhead_Cycles</td><td>1</td><td>1</td></tr><tr><td>Address_Bits</td><td>32</td><td>32</td></tr><tr><td>Sim_Time</td><td>1.0</td><td>1.0</td></tr></table> <h2>AMBA_AHB4</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_4&quot;</td><td>&quot;AHB_Bus_4&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_4_Port_1&quot;, &quot;AHB_Bus_4_Port_2&quot;, &quot;AHB_Bus_4_Port_3&quot;, &quot;AHB_Bus_4_Port_4&quot;, &quot;AHB_Bus_4_Port_5&quot;, &quot;AHB_Bus_4_Port_6&quot;, &quot;AHB_Bus_4_Port_7&quot;, &quot;AHB_Bus_4_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>AMBA_AHB3</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_3&quot;</td><td>&quot;AHB_Bus_3&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_3_Port_1&quot;, &quot;AHB_Bus_3_Port_2&quot;, &quot;AHB_Bus_3_Port_3&quot;, &quot;AHB_Bus_3_Port_4&quot;, &quot;AHB_Bus_3_Port_5&quot;, &quot;AHB_Bus_3_Port_6&quot;, &quot;AHB_Bus_3_Port_7&quot;, &quot;AHB_Bus_3_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>AMBA_AHB2</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_2&quot;</td><td>&quot;AHB_Bus_2&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_2_Port_1&quot;, &quot;AHB_Bus_2_Port_2&quot;, &quot;AHB_Bus_2_Port_3&quot;, &quot;AHB_Bus_2_Port_4&quot;, &quot;AHB_Bus_2_Port_5&quot;, &quot;AHB_Bus_2_Port_6&quot;, &quot;AHB_Bus_2_Port_7&quot;, &quot;AHB_Bus_2_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>AMBA_AHB</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;AHB_Bus_1&quot;</td><td>&quot;AHB_Bus_1&quot;</td></tr><tr><td>Bus_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>_explanation</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td><td>Interfaces and Buses-&gt;AMBA-&gt;AMBA_AHB_Bus</td></tr><tr><td>Burst_Size_Bytes</td><td>64</td><td>64</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr><tr><td>FIFO_Buffers</td><td>8</td><td>8</td></tr><tr><td>Round_Robin_Port_Array</td><td>{Bus_Name+&quot;_Port_1&quot;, Bus_Name+&quot;_Port_2&quot;, Bus_Name+&quot;_Port_3&quot;, Bus_Name+&quot;_Port_4&quot;, Bus_Name+&quot;_Port_5&quot;, Bus_Name+&quot;_Port_6&quot;, Bus_Name+&quot;_Port_7&quot;, Bus_Name+&quot;_Port_8&quot;}</td><td>{&quot;AHB_Bus_1_Port_1&quot;, &quot;AHB_Bus_1_Port_2&quot;, &quot;AHB_Bus_1_Port_3&quot;, &quot;AHB_Bus_1_Port_4&quot;, &quot;AHB_Bus_1_Port_5&quot;, &quot;AHB_Bus_1_Port_6&quot;, &quot;AHB_Bus_1_Port_7&quot;, &quot;AHB_Bus_1_Port_8&quot;}</td></tr><tr><td>Devices_Attached_to_Slave_by_Port</td><td>{{&quot;Device_1&quot;},{&quot;Device_2&quot;},{&quot;Device_3&quot;},{&quot;Device_4&quot;},{&quot;Device_5&quot;},{&quot;Device_6&quot;},{&quot;Device_7&quot;},{&quot;Device_8&quot;}}</td><td>{{&quot;Device_1&quot;}, {&quot;Device_2&quot;}, {&quot;Device_3&quot;}, {&quot;Device_4&quot;}, {&quot;Device_5&quot;}, {&quot;Device_6&quot;}, {&quot;Device_7&quot;}, {&quot;Device_8&quot;}}</td></tr></table> <h2>TaskGenerator</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Name</td><td>&quot;H_264&quot;</td><td>&quot;H_264&quot;</td></tr><tr><td>Mode_of_Operation</td><td>&quot;Loop&quot; /* Field gets input, Random selects a Task, Loop is sequential */</td><td>&quot;Loop&quot;</td></tr><tr><td>DEBUG</td><td>false /* To Debug Port */</td><td>false</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;TaskGenerator</td><td>ProcessorGenerator-&gt;TaskGenerator</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr><tr><td>Instruction_Mix_File</td><td>Instruction_Mix_Table.txt</td><td>&quot;Instruction_Mix_Table.txt&quot;</td></tr></table> <h2>DMA</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr></table> <h2>ARM9_Instruction_Set</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td><td>This is the Instruction Set for ARM9 : Reference ARM TRM manual. \\n</td></tr><tr><td>Instruction_Set_Name</td><td>&quot;ARM_INSTR&quot;</td><td>&quot;ARM_INSTR&quot;</td></tr><tr><td>_explanation</td><td>ProcessorGenerator-&gt;Instruction_Set</td><td>ProcessorGenerator-&gt;Instruction_Set</td></tr><tr><td>Instruction_Set_Text</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC VPU ; /* two execution units */\\n EXEC INT_1 ; /* ARM execution unit */\\n VPU INT_2 ; /* MOVE execution unit */\\n\\nbegin INT_1 ;\\n ADD 1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;\\n\\nbegin INT_2 ;\\n UMRC 1 ; /* mapped to MRC */\\n UMCR 1 ; /* mapped to MCR */\\n UMBBR 1 ; /* mapped to MRC */\\n UMRBB 1 ; /* mapped to MCR */\\n UBBLD 1 ; /* mapped to LDC */\\n USALD 2 3 ; /* mapped to LDC. depends on CR_BYO */\\nend INT_2 ;\\n</td><td>/* Instruction Set : Reference ARM TRM manual. */\\n\\n Mnew Ra Rb Rc Rd Re Rf Rg Rh; /* Label */\\n ARM EXEC VPU ; /* two execution units */\\n EXEC INT_1 ; /* ARM execution unit */\\n VPU INT_2 ; /* MOVE execution unit */\\n\\nbegin INT_1 ;\\n ADD 1 ;\\n MV_MOV 1 4 ; /* group MOVE */\\n MV_MVN 1 4 ;\\n MV_MRS 1 2 ;\\n MV_MSR 3 ;\\n\\n ART_ADD 1 4 ; /* group ARITHMETIC */\\n ART_ADC 1 4 ;\\n ART_SUB 1 4 ;\\n ART_SBC 1 4 ;\\n ART_RSB 1 4 ;\\n ART_RSC 1 4 ;\\n ART_MUL 2 3 ;\\n ART_MLA 2 3 ;\\n ART_MULS 4 ;\\n ART_MLAS 4 ;\\n ART_UMULL 3 4 ;\\n ART_UMLAL 3 4 ;\\n ART_SMULL 3 4 ;\\n ART_SMLAL 3 4 ;\\n ART_UMULLS 5 ;\\n ART_UMLALS 5 ;\\n ART_SMULLS 5 ;\\n ART_SMLALS 5 ;\\n ART_CMP 1 4 ;\\n ART_CMN 1 4 ;\\n ART_QADD 1 2 ;\\n ART_QSUB 1 2 ;\\n ART_SMULXY 1 ;\\n ART_SMULAXY 2 ;\\n ART_SMULWX 1 ;\\n ART_SMULAWX 2 ;\\n ART_SMULALX 2 3 ;\\n ART_CLZ 1 ;\\n\\n LGL_TST 1 4 ; /* group LOGICAL */\\n LGL_TEQ 1 4 ;\\n LGL_AND 1 4 ;\\n LGL_EOR 1 4 ;\\n LGL_ORR 1 4 ;\\n LGL_BIC 1 4 ;\\n\\n *BR_B 3 ; /* group LOGICAL */\\n BR_BL 3 ; \\n BR_BX 3 ;\\n BR_BLX 3 ;\\n\\n LD_LDR 1 5 ; /* group LOAD */\\n LD_LDRT 1 5 ; \\n LD_LDRB 1 5 ; \\n LD_LDRBT 1 5 ; \\n LD_LDRSB 1 5 ; \\n LD_LDRH 1 5 ; \\n LD_LDRSH 1 5 ; \\n LD_LDM_PC 5 ; \\n LD_LDM 1 12 ; /* number of registers */\\n\\n STR_STR 1 ; /* group STORE */\\n STR_STRT 1 ; \\n STR_STRB 1 ; \\n STR_STRBT 1 ; \\n STR_STRH 1 ;\t\\n STR_STM_PC 1 2 ;\\n STR_STM 1 12 ; /* number of registers */\\n\\n MISC_SWP 3 ; /* group MISCELLANEOUS */\\n MISC_SWI 3 ; \\n MISC_BKPT 3 ; \\n\\nend INT_1 ;\\n\\nbegin INT_2 ;\\n UMRC 1 ; /* mapped to MRC */\\n UMCR 1 ; /* mapped to MCR */\\n UMBBR 1 ; /* mapped to MRC */\\n UMRBB 1 ; /* mapped to MCR */\\n UBBLD 1 ; /* mapped to LDC */\\n USALD 2 3 ; /* mapped to LDC. depends on CR_BYO */\\nend INT_2 ;\\n</td></tr><tr><td>Record_Set_Name</td><td>&quot;Record_Set_Name&quot;</td><td>&quot;Record_Set_Name&quot;</td></tr><tr><td>Memory_Type</td><td>Global</td><td>Global</td></tr></table> <h2>ARM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td><td>Mapping of ARM9 CPU architecture parameters to generic CPU\\nPlease NOTE that this is not goldenized and is only for Demo purpose.\\n</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Processor_Name</td><td>&quot;ARM926&quot;</td><td>&quot;ARM926&quot;</td></tr><tr><td>Processor_Setup</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: 100.0\\nContext_Switch_Cycles: 10 /* switch between internal pipeline stages */\\nInstruction_Queue_Length: 100 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages: 5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units: 2 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units: 0 /* no particular FP units */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=100.0, Size_KBytes=16, Words_per_Cache_Line=8, Cache_Miss_Name=sdr} \\nD_1: {Cache_Speed_Mhz=100.0, Size_KBytes=16, Words_per_Cache_Line=8, Cache_Miss_Name=sdr} \\n</td><td>/* First row contains Column Names. */\\nParameter_Name Parameter_Value ;\\nProcessor_Instruction_Set: ARM_INSTR\\nNumber_of_Registers: 16 /* active registers being processed. total reg = 31 */\\nProcessor_Speed_Mhz: 100.0\\nContext_Switch_Cycles: 10 /* switch between internal pipeline stages */\\nInstruction_Queue_Length: 100 /* This cab be assumed. Real ARM data ? */\\nNumber_of_Pipeline_Stages: 5 /* after 5\\'th stage is implemeted */\\nNumber_of_INT_Execution_Units: 2 /* 1 exection unit 1 coproc unit */\\nNumber_of_FP_Execution_Units: 0 /* no particular FP units */\\nNumber_of_Cache_Execution_Units: 2 /* I-cache and D-cache */\\nI_1: {Cache_Speed_Mhz=100.0, Size_KBytes=16, Words_per_Cache_Line=8, Cache_Miss_Name=sdr} \\nD_1: {Cache_Speed_Mhz=100.0, Size_KBytes=16, Words_per_Cache_Line=8, Cache_Miss_Name=sdr} \\n</td></tr><tr><td>Pipeline_Stages</td><td>/* Pipeline stages in ARM */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_DECODE I_1 wait none ; /* Decode */\\n3_EXECUTE ARM exec none ; /* Execute ARM instr */\\n4_MEMORY ARM wait none ; /* Wait for ARM instr */\\n5_MEMORY D_1 write none ; /* Write */</td><td>/* Pipeline stages in ARM */\\nStage_Name Execution_Location Action Condition ; \\n1_FETCH I_1 instr none ; /* Fetch */\\n2_DECODE I_1 wait none ; /* Decode */\\n3_EXECUTE ARM exec none ; /* Execute ARM instr */\\n4_MEMORY ARM wait none ; /* Wait for ARM instr */\\n5_MEMORY D_1 write none ; /* Write */</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Processor_Bits</td><td>32</td><td>32</td></tr></table> <h2>Timing_Diagram</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Proc_Name</td><td>&quot;ARM926&quot;</td><td>&quot;ARM926&quot;</td></tr><tr><td>Bus_Name</td><td>&quot;Bus_1&quot;</td><td>&quot;Bus_1&quot;</td></tr><tr><td>Cache_Name</td><td>&quot;Cache_1&quot;</td><td>&quot;Cache_1&quot;</td></tr><tr><td>DRAM_Name</td><td>&quot;sdr&quot;</td><td>&quot;sdr&quot;</td></tr><tr><td>AXI_Name</td><td>&quot;AXI_1&quot;</td><td>&quot;AXI_1&quot;</td></tr><tr><td>Memory_Controller_Name</td><td>&quot;LPDDR_1&quot;</td><td>&quot;LPDDR_1&quot;</td></tr><tr><td>HW_DRAM_Name</td><td>&quot;SDRAM&quot;</td><td>&quot;SDRAM&quot;</td></tr><tr><td>_explanation</td><td>Hardware Setup-&gt;Timing_Diagram</td><td>Hardware Setup-&gt;Timing_Diagram</td></tr><tr><td>Sim_Time</td><td>Ntime</td><td>1.0E-3</td></tr></table> <h2>DRAM</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Memory_Name</td><td>&quot;sdr&quot;</td><td>&quot;sdr&quot;</td></tr><tr><td>Memory_Speed_Mhz</td><td>100.0</td><td>100.0</td></tr><tr><td>Memory_Size_MBytes</td><td>64.0</td><td>64.0</td></tr><tr><td>Access_Time</td><td>&quot;Read 10.0, Prefetch 6.0, Write 10.0, ReadWrite 8.0, Erase 9.0&quot;</td><td>&quot;Read 10.0, Prefetch 6.0, Write 10.0, ReadWrite 8.0, Erase 9.0&quot;</td></tr><tr><td>FIFO_Buffers</td><td>32</td><td>32</td></tr><tr><td>Refresh_Rate_Cycles</td><td>1638400</td><td>1638400</td></tr><tr><td>Refresh_Cycles</td><td>32</td><td>32</td></tr><tr><td>Memory_Address</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td><td>&quot;/* Format: Min_Address,Max_Address. Example:201,300 */&quot;</td></tr><tr><td>Controller_Time</td><td>&quot;Cycle_Time * 1.0&quot;</td><td>&quot;Cycle_Time * 1.0&quot;</td></tr><tr><td>Enable_Hello_Messages</td><td>true</td><td>true</td></tr><tr><td>Width_Bytes</td><td>4</td><td>4</td></tr><tr><td>Memory_Type</td><td>SDR</td><td>SDR</td></tr><tr><td>refresh</td><td>false</td><td>false</td></tr></table> <h2>Architecture_Setup</h2><table border="1"><tr><td><b>Parameter</b></td><td><b>Expression</b></td><td><b>Value</b></td></tr><tr><td>Block_Documentation</td><td>Enter User Documentation Here</td><td>Enter User Documentation Here</td></tr><tr><td>Architecture_Name</td><td>&quot;Architecture_1&quot;</td><td>&quot;Architecture_1&quot;</td></tr><tr><td>Field_Name_Mapping</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td><td>/* First row contains Column Names. */\\nExternal_Field_Name Internal_Field_Name ; \\nA_Address A_Address ; \\nA_Bytes A_Bytes ; \\nA_Data A_Data ; \\nA_IDX A_IDX ; \\nA_Instruction A_Instruction ; \\nA_Priority A_Priority ; \\nA_Source A_Source ; \\nA_Destination A_Destination ; \\nA_Task_ID A_Task_ID ; \\nA_Time A_Time ; \\n</td></tr><tr><td>Routing_Table</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nDMA\t\tTrigger\t\tDMA\t\tDout ;</td><td>/* First row contains Column Names. */\\nSource_Node Destination_Node Hop Source_Port ; \\nDMA\t\tTrigger\t\tDMA\t\tDout ;</td></tr><tr><td>Number_of_Samples</td><td>2</td><td>2</td></tr><tr><td>Statistics_to_Plot</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td><td>&quot;Processor_1_PROC_Utilization_Min, Processor_1_PROC_Utilization_Mean, Processor_1_PROC_Utilization_Max&quot;</td></tr><tr><td>Internal_Plot_Trace_Offset</td><td>2</td><td>2</td></tr><tr><td>Listen_to_Architecture_Options</td><td>Pipeline</td><td>Pipeline</td></tr></table>

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