HardwareDevices / DMA
Block Name: DMA
Code File Location: VisualSim/actor/lib/bus/DMA_Controller
Description
DMA block that represents a memory controller that sits between the Processor or bus or DeviceInterface Block and the Memory bank. The DeviceInterface acts as an intermediate block and just transfers the transactions from bus or DMA to appropriate memory bank or devices connected to the DeviceInterface. DeviceInterface receives the response from memory bank or devices and transfers it back to the bus/DMA. The DeviceInterface can be connected to either a Linear or Point to Point bus.
With Internal mode of operation, the transactions received at Req port are sent to the appropriate memory banks or devices connected to bus ports that exists below the DeviceInterface; i.e bus ports connected to the input port of the DeviceInterface block. With Custom mode of operation the transactions received at Req port are sent to the Ack port, for the user to manipulate. The transaction can be routed back to the DeviceInterface through the Din input port. The response from the memory or device is sent out from the Dout output port. Both the incoming and outgoing transactions are delayed by the number of cycles specified in DMA_to_Device_Cycles and Device_to_DMA_Cycles respectively. The DeviceInterface can also be used as a simple bridge between two buses.
DMA
Controller will do sequential operation. This means if we have to do a
"Read" from "DRAM" and do a "Write" to "Display" ( data size = 1024
bytes, burst word size = 64 bytes ). So since data size is > burst
word size , the packets will be sent out in fragments. Fragment1_Read,
Fragment_1_Write,Fragment2_Read,Fragment2_Write ... etc
The
DMA controller actions can either be defined in a database or be
defined in the incoming data structure ( the data structure coming in
on the request port ). For following the actions listed in Database
block , user has to specify the database name in the parameter "Memory_Database_Reference".
If the user wishes to define the actions for the DMA from Data
Structure then put the value forparameter "Memory_Database_Reference" as "None".
If the user wants to define actions for the DMA from Data structure fields, then following fields are necessary :
A_DMA_Command = {"Read","Write"} /* Specify sequential actions in array*/
A_DMA_Destination = {"RAM","Display"} /* Specify the destination for sequential actions in array */
A_Priority = 1 /* Specify the priority for this Task */
A_DMA_Bytes = {1024,1024} /* Specify the data size for sequential actions in array */
A_DMA_Channel = {1,1} /* Specify the channel for the task */
A_DMA_Burst_Bytes = {64,64} /* Specify the burst word size for the task*/
The DMA controller provides user with the Traces as well.
The data structure coming out from dout port will be having two added fields : Task_Latency ( which gives the latency for the task completed ) and Task_Throughput ( which gives the throughput for the task )
If the user wishes to configure the DMA to perform outstanding operations ( that is, send out requests without waiting for the acknowledgement ), then it can be done by configuring a parameter called Outstanding_Req_Count. This parameter is of Integer Array type and each index corresponds to each channel. Each channel can have a max outstanding request count corresponsing to the value entered here.
If there are large number of DMA channels, for example 64 and if the user wishes to keep the outstanding requests from each channel to 1, thenOutstanding_Req_Count can be given the value as an empty array -> {}.
To illustrate the usage, look at the following Examples in the BDE.
Timing Details:
4 cases are there :
- Single Read request
- Transaction at Last word from AXI
1 cycle delay to send it
out on Ack port if DMA channel is not busy
1 cycle delay when it comes
back before sending it out on dout port
- Transaction at First word from AXI
1 cycle delay to
send it out on Ack port if DMA channel is not busy
n cycle delay ( according to
packet size) when it comes back before sending it out on dout port
- Single Write request
- Transaction at Last word from AXI
n cycle delay ( according
to packet size) to send it out on Ack port if DMA channel is not busy
1 cycle delay when it comes
back before sending it out on dout port
- Transaction at First word from AXI
n cycle delay (
according to packet size) to send it out on Ack port if DMA channel is not busy
1 cycle delay when it comes
back before sending it out on dout port
- Read Write sequence
- Transaction at Last word from AXI
1 cycle delay to send it
out on Ack port if DMA channel is not busy for read
1 cycle delay when it comes
back + n cycle delay ( according to packet size) for write
1 cycle delay when write
response comes back. Then check whether sequence is task is completed. Else
read after 1 cycle delay and this continues till task is completed
- Transaction at First word from AXI
1 cycle delay to send it
out on Ack port if DMA channel is not busy for read
n cycle delay ( according
to packet size) when it comes back + n cycle delay ( according to packet size)
for write
1 cycle delay when write response
comes back. Then check whether sequence is task is completed. Else read after 1
cycle delay and this continues till task is completed
- Write Read sequence
- Transaction at Last word from AXI
n cycle delay ( according
to packet size) to send it out on Ack port if DMA channel is not busy for read
1 cycle delay when it comes
back + 1 cycle delay for Read
1 cycle delay when Read
response comes back. Then check whether sequence is task is completed. Else
Write after n cycle delay ( according to packet size) and this continues till
task is completed
- Transaction at First word from AXI
n cycle delay ( according
to packet size) to send it out on Ack port if DMA channel is not busy for read
1 cycle delay when it comes
back + 1 cycle delay for Read
n cycle delay ( according to
packet size) when Read response comes back. Then check whether sequence is task
is completed. Else Write after n cycle delay ( according to packet size) and
this continues till task is completed
See Also:
Serialized Form
| Parameter |
Explanation | Type |
Example |
| Architecture_Name | Unique Name of the Architectural block, allows multiple architecture representations in the same model. | String | "Architecture_1" |
| DMA_Controller_Name | Unique Name of the DMA block, allows for multiple DeviceInterface in the same model, names differentiate instances. | String | "DMA_Controller_1" |
| Memory_Database_Reference | Name
of the Database block that has the DMA setup details or put it as "None" if vaules are read from the field |
String | "MyDatabase_1" |
| DMA_to_Device_Cycles | DMA_to_Device_Cycles is the Cycles taken to send data from DMA to memory or device. The parameter value can be either a Control_Expression_or_DS_Fld_Name_or_Integer. If a RegEx is specified the result of the regular expression is used as parameter value. If a Data Structure field name is specified the incoming Data Structure's field value will be used as parameter value. An integer value- number of cycles can also be specified like 100. | Integer | RegEx_or_None |
| Device_to_DMA_Cycles | Device_to_DMA_Cycles is the Cycles taken to send data from memory or device to DMA_Controller. The parameter value can be either a Control_Expression_or_DS_Fld_Name_or_Integer. If a RegEx is specified the result of the regular expression is used as parameter value. If a Data Structure field name is specified the incoming Data Structure's field value will be used as parameter value. An integer value- number of cycles can also be specified like 100. | Integer | RegEx_or_None |
| Channel_FIFO_Buffers | Channel FIFO buffer of the Channel input, output queue that stores the transactions flowing in and out. An integer value for the size of Channel FIFO buffer can be specified like 20. | Integer | Integer |
| Speed_Mhz | Speed_Mhz is the Speed of execution of the Controller in Mhz. A double value for the Speed in Mhz can also be specified like 500.0. | double | Double |
| DMA_Channels | The number of DMA channels. | Integer | 8 |
| Outstanding_Req_Count |
The number of oustadning requests per channel |
{Integer} |
{8,8,8,8,8,8,8,8} -> 8 outstanding requests per channel |
| Width_Bytes | The
Word Width in bytes. Replaced pull down option with line option so that the options are not limited. |
Integer | 4 |
| Port | Explanation |
| request | Request Input port. |
| din | Data In - Input port. |
| ack | Acknowledge Output port. |
| dout | Data out - Output port. |
| reject | Output port to drop transactions when DMA queue is full. |