Power Digital Twin replaces present in-accurate, expensive and time-consuming method of power analysis such as use of spreadsheets, logic or board-level simulation and prototypes. These methods are limited in system capacity scope and very late in the design process. VisualSim Power Digital Twin can simulate a full SoC in 15 minutes and a full vehicle in 30 minutes to generate the performance-power metrics and conduct architecture trade-offs.
Power Metrics can be tracked at every instant of time and generate consolidated power, average, cumulative, battery lifecycle and thermal characteristics for heat and temperature. System designers can save huge amounts of time and enabling them to innovate further on features and functions of the systems in offering better solutions than the competitor. The clear whole picture of power activity is presented for actionable design changes at architecture level. VisualSim provides thermal information to thermal/mechanical engineers to effectively design cooling systems and mechanical structures of the device to handle the rise in temperatures.
Deliver power estimates for all hardware/Silicon IP/Network blocks, software/program code execution and network data flow tasks. By having complete power analytics picture of the system, designers can improve the total power efficiency of the system in budgeting the available power to each functional block to operate at different states of standby, sleep, low power, turbo-boost and any custom modes to deliver optimized performance and power distributions at its best. In the present software centric systems VisualSim enables tracking the power flow while running the different software programs for all types of conditions.
Semiconductor SOC chip designs are continuously moving towards deeper nodes such as 3 nm and even lower, where each node brings performance and power improvement in the range of 20-30%. Each node shrink require complete power and performance analysis at architecture stage. Power Digital Twin enables rapid regression for different semiconductor process nodes, clock speeds and other configuration using complex expressions.
VisualSim is designed to provide time-to-market advantage to its customers from its first version of the product to the whole series of upgrades by significantly bringing down development time using the same base architecture effectively.
Mirabilis provide full support during initial implementation for seamless migration to VisualSim based solutions. Along with providing rich and large IP of fully updated functional models, Mirabilis quickly integrate any custom function models for cutting edge applications such as Tensor processing elements, GPU, NPU and such AI computing elements in your processor architecture. Mirabilis solutions fully support chiplet based 3D IC design.
The tool features support for latest standards such as SystemVerilog and a power domain specific standard called Unified Power Format (UPF). VisualSim Generates UPF input file, VCD and SystemVerilog for Unified Verification Methodology.