Power consumption can be reduced in several ways, including the following:
• Voltage reduction – dual-voltage CPUs, dynamic voltage scaling, under-voltage, etc.
• Frequency reduction – under-clocking, dynamic frequency-scaling, etc.
• Capacitance reduction – increasingly integrated circuits that replace PCB traces between two chips with relatively lower-capacitance on-chip metal interconnect between two sections of a single integrated chip; low-k dielectric, etc.
• Power gating techniques such as clock gating and globally asynchronous locally synchronous, which can be thought of as reducing the capacitance switched on each clock tick, or can be thought of as locally reducing the clock frequency in some sections of the chip.
• Various techniques to reduce the switching activity – number of transitions the CPU drives into off-chip data buses, such as non-multiplexed address bus, bus encoding such as Gray code addressing, or value cache encoding such as power protocol. Sometimes an “activity factor” (A) is put into the above equation to reflect activity.
• Sacrificing transistor density for higher frequencies.
• Layering heat-conduction zones within the CPU framework (“Christmasing the Gate”).
• Recycling at least some of that energy stored in the capacitors (rather than dissipating it as heat in transistors) – adiabatic circuit, energy recovery logic, etc.
• Optimizing machine code – by implementing compiler optimizations that schedules clusters of instructions using common components, the CPU power used to run an application can be significantly reduced.
VisualSim can model these CPU power reductions with the Power_Manager as the baseline block.
Web: https://en.wikipedia.org/wiki/Processor_power_dissipation