While performance is the key factor for commercial success of any semiconductor chip, the development cost and time plays an even more critical role in the successful launch of the chip. Extremely complex and expensive semiconductor fabrication technologies such as nano-sheet FETs are used today at 3 nm and 2 nm technology nodes. Due to which the development cost of complex monolithic SoC made at these nodes is spiraling to unacceptable levels, suggesting complete SoC on a monolithic silicon die is no longer economically-feasible. It is becoming extremely challenging to achieve acceptable production yield rate by the most advanced semiconductor chip foundries for large die size monolithic chips. IP functional blocks such as analog, power management and interface reap no benefits at deep nodes; alternatively making them at mature nodes such as 28nm is more beneficial. With economy of scale not working for monolithic ICs, Chip industry is rapidly migrating to multi-die heterogeneous integration of dies from different vendors made at different nodes packaged in a single 3D and 2.5D chips. This trend throws big challenge of advanced packaging as well as increase in complexity of design. Stakeholders in this industry have come together to find common standards for this fast-emerging market. Universal Chiplet Interconnect Express (UCIe) is the new die-to-die (D2D) interconnect open-standard widely adopted by the semiconductor industry.
To address the multifaceted challenges of designing multi-die SoC, Mirabilis Design provides an EDA software solution named VisualSim Architect to simulate the complete SoC performance virtually and run all the tests similar to running on the physical product. The latest VisualSim Architect integrates full support for UCIe based heterogeneous 3D semiconductor development for range of applications. VisualSim UCIe supports the latest updates, timing, and power of proprietary and commercial 3D UCIe IP.
Overview of VisualSim Architect
VisualSim Architect creates high level architecture models using a combination of stochastic as well as more detailed cycle-accurate system-level IP blocks. This is the only system-design software tool which allows use of both stochastic and cycle accurate models to create an environment in which your chip design to be operated close to real conditions. The inherent strength of VisualSim Architect is it covers system modeling of complete end-user systems such as full automotive vehicle, subsystem, a complete SoC chip and individual semiconductor IP inside the chip. In that sense, VisualSim Architect is the best software to design both monolithic and heterogeneous SoC, which is a system of systems (sub). It has become an industry norm to use system modeling software by leading semiconductor companies to create working model of the product at the early stage of the product design enabling full visibility of the system, applying shift-left and shift-right design methodology and cost-effective design-reuse of the base model.
VisualSim Architect solves multiple design challenges typically faced in designing heterogeneous 3D semiconductor IC:
Architecture and topology:
Engineers now have the option to choose multiple compute architectures such as CPU, GPU, TPU, DSP and accelerators, to achieve the set goal of computing with optimized utilizations of resources with minimal bottlenecks. There are multiple choices of network topologies to interconnect Masters, Slaves and memory. VisualSim Architect provides detailed comparative metrics of performance of each network and topology leading to the best choice. The feasibility of any new innovative architecture can be evaluated by looking into performance analysis meeting the design-goal.
D2D interconnect:
UCIe makes Chiplets interoperable and works across process nodes. UCIe is fully compatible with PCIe6 and other streaming protocols (AXI, CMN600, Tilelink, and CHI). The models representing these communication protocols can be configured as per vendor specific specification parameters. VisualSim Architect delivers performance statistics for these different communications protocols to arrive at best protocol or mix of protocols.
Power Analysis:
Power Metrics can be tracked at every instance of time and generate consolidated power, average, cumulative for each IP, die/chiplet and for the whole chip. The clear whole picture of power activity is presented for actionable design changes at architecture level. Whenever the users notice peak power at a particular instant of time, they can view overall performance of system to know what functional blocks are on and the power they are consuming and do the design changes to reduce the peak power.
Thermal Analysis:
VisualSim Architect does dynamic calculation while the performance simulation is running providing thermal characteristics at all instance of time. Thermal engineers have all the information on heat generation pattern and can take thermal dissipation action on each chiplet and alert the electrical designer to reduce the power flow to the part of the device. VisualSim Architect enables thermal, mechanical and electrical engineers to work together during specification-stage rather than at implementation stage. Any change in architectural design will instantly change related thermal data.
Cache Coherency:
In a multi-processor and multi-chiplets with common cache memory, VisualSim Architect enables designing memory cache coherency and application partitioning across dedicated dies for CPU, GPU, TPU and AI Engines.
Packaging:
VisualSim Architect’ performance-analysis helps to figure out die-sizes and placement of dies to ensure optimal utilization of real-estate available in the whole package. To address the packaging challenges of multi-die SoC, VisualSim Architect generates performance statistics for different packaging options.
Security:
Third party chiplets pose security threat, where they may hold malicious block of IP injecting bugs and reading protected data from other chiplets/dies. VisualSim performance analysis helps in investigating unexpected power-spikes and any abnormal data-flow to find out data-manipulation, brute-force attacks and any such hardware related threats.
IP Library:
Designers have access to the extensive VisualSim IP library of both Semiconductors and systems to create models of the IP, SoC, flight systems, networks, data centers, automotive systems, vehicles, radars, communication systems and other electronics.
VisualSim provide advantage of design-reuse of first version of SoC to develop upgraded and enhanced versions of SoCs by significantly bringing down development time using the same base architecture effectively. Models constructed using this new 3D solution can compare the performance of chiplets versus monolithic SoC, get latency and power measurements for different applications, scalability of solutions with growing application complexity, optimal partitioning choices using the ARM Chiplet System Architecture, and enabling chiplet reuse.
Let’s take the example of designing the multi-die SoC for autonomous driving in automotives as shown in the picture below. It will typically have AI engine tiles, GPU, processor subsystem, memory chiplet and UCIe D2D interconnect. Performance analysis using VisualSim Architect answers to design consideration questions such as mesh size and sample size of AI Tile, selection of protocol, location of memory and processor chiplets, number of lanes, clock speeds and FLIT Size. VisualSim Architect can address design issues within the die and inside the full chip.