Cortex M4 Microcontrollers

Architecture model of the energy efficient ARM microcontrollers

ARM Processor

  • Cortex M0 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • Cortex M3 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • Cortex M4 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • A7
    Power-performance model
  • A8
    Highly optimized for performance and power efficiency
  • A9
    32-bit processor core
  • A53
    Enables Multi-Core power efficient ARMv8 processor
  • A72
    Enables Multi-Core high performance 64-bit ARMv8 processor
  • R4
    Multi-Core 5G baseband SoC processor

Quick Explanation

  • Supports a 3 level pipeline
  • Supports execution of floating point instructions
  • Supports preemption
  • Supports AMBA interface
  • Supports multiple memory interfaces
  • ARMv7-E instruction set
  • Support FPU
  • 240 interrupts available
  • 12 cycle interrupt latency.
  • Integrated sleep modes.

Protocol

  • ARM Cortex M4 + FPU

Model Link

Cortex M4- 3 stage pipelined processor