Cortex M0 Microcontrollers

Architecture model of the energy efficient Arm micro-controllers

ARM Processor

  • Cortex M0 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • Cortex M3 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • Cortex M4 Microcontrollers
    Architecture model of the energy efficient ARM microcontrollers
  • A7
    Power-performance model
  • A8
    Highly optimized for performance and power efficiency
  • A9
    32-bit processor core
  • A53
    Enables Multi-Core power efficient ARMv8 processor
  • A72
    Enables Multi-Core high performance 64-bit ARMv8 processor
  • R4
    Multi-Core 5G baseband SoC processor

Quick Explanation

  • Supports a 3-stage pipeline
  • Also supports 2-stage pipeline for reduced power consumption
  • Supports preemption
  • Supports AMBA interface
  • Support interrupt
  • 16-bit and 32-bit
  • ARMv6-M instruction set
  • 32-bit hardware integer multiply with 32-bit result
  • 1 to 32 interrupts

Protocol

  • ARM Cortex M0

Cortex M0 - 3-Stage Pipelined Processor