IBM and Xilinx version supported for use as internal memory. Also support 60X bus
VisualSim CoreConnect supports both the IBM and the Xilinx variations of the protocol implementation. The CoreConnect integrates with the PowerPC, other IO and memory models available standard in VisualSim library. The library includes the PLB, OPB and the bridges. Also, the block has interfaces for processors, DSP, IOs and memory controllers. The bus supports blocking and non-blocking, supports multi-PLB requests per cycle, and has both single transfer and burst transfer mode of operations. The purpose of this library is to assemble a complete SoC or FPGA for conducting performance analysis and to design around the PLB bus for high-performance systems.
The library contains a large array of testing tools for verifying the correctness off the system. These include the large traffic and queuing models shipped with VisualSim, the application templates for use in different industries and different modes of operation, detailed tracing, and analytics. The library is completely open and unencrypted. This means that the user can freely modify any internal details of the CoreConnect buses and arbiters. There are standard parameters at the Master and Slave, interface to modify the arbiter, and transaction flows.
Some of the importantparameters for the CoreConnect block are as follows: Bus speed, Burst speed, FIFO buffers etc……
The Processor Local Bus(PLB) protocol is a high performance bus for interconnecting processor, memory subsystems and high bandwidth peripherals. Some of the key features of CoreConnect are as follows:
CoreConnect is a microprocessor bus architecture for System-on-Chip(SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. Elements of this architecture includes the Processor Local Bus(PLB), the On-chip Peripheral Bus(OPB), a bus bridge and a Device Control Register(DCR) bus. High performance peripherals connect to the high bandwidth, low latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB.