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Benefits

  • Full RISC-V Ecosystem Support – Integrated with SiFive and other vendors.
  • TileLink Switch – Scales interconnect performance for large SoCs.
  • Interoperability – Works alongside AMBA, AXI, PCIe, and NoCs.
  • System-Level Validation – Latency, throughput, and congestion analysis.
  • Future-Proofing – Support for open, flexible SoC designs.

The TileLink block in VisualSim models a high-performance interconnect protocol for multi-core and RISC-V–based systems. TileLink enables scalable, cache-coherent communication between processors, memory, and peripherals, making it well-suited for open-source SoCs and next-generation heterogeneous architectures. VisualSim also contains a TileLink Switch and Coherency across the TileLink bus and Switch.

While TileLink adoption is niche compared to AMBA or PCIe, it remains strategically important in the RISC-V ecosystem. VisualSim has integrated TileLink into models from multiple RISC-V vendors, including SiFive, and has developed a TileLink switch to support complex SoC interconnects.

Overview

  • Request Initiation – Masters send requests to target components.
  • Response Handling – Slaves reply with data or status.
  • Traffic Buffering – Temporary storage smooths out bursty communication.
  • Cross-Protocol Support – Can bridge with AMBA, AXI, and PCIe.
  • Performance Metrics – Latency, throughput, and arbitration analysis.

Supported Standards

  • TileLink (TL-UL, TL-C, TL-H) variants
  • Compatibility with RISC-V SoC design flows

Key Parameters

  • TileLink_Speed_MHz – Operating frequency.
  • Number_Masters – Number of initiators.
  • Number_Slaves – Number of targets.

Parameter Snapshots

  • Tilelink Parameter

Simulation Results

  • Latency and Throughput Analysis
  • Traffic Congestion Studies
  • Cache Coherency Validation
  • Switch Arbitration Studies
  • Latency
  • Tilelink Plot

Application

  • RISC-V SoCs – Communication between SiFive or other vendor cores and peripherals.
  • Chiplet Architectures – TileLink used as die-to-die interconnect in modular designs.
  • Cache-Coherent Systems – Multi-core designs requiring synchronized memory access.
  • Hybrid SoCs – Integrating TileLink with NoC or AMBA fabrics.
  • Research & Academia – Open-source processor exploration.

Integrations

  • SiFive and other RISC-V vendors.
  • Works with RISC-V cores, caches, DMA, and memory controllers.
  • Bridges with NoCs and other interconnects for hybrid architectures.

View Demo

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