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Benefits

  • Leadership in RISC-V – Used for both processor design and real-world application simulation.
  • Full ISA & Extensions Support – From base to custom instructions.
  • Software Validation Before Silicon – Run real code via Spike ISS traces.
  • Scalable Exploration – From small embedded cores to multi-core OoO processors.
  • Energy-Aware Modeling – Optimize performance per watt.
  • Cross-Domain Utility – Applicable to automotive, AI, IoT, HPC, and aerospace systems.

The RISC-V architecture in VisualSim provides a comprehensive environment for simulating and analyzing RISC-V processor behavior. It includes support for the full RISC-V ISA, covering 32-bit and 64-bit architectures, and models ranging from In-Order pipelines to advanced Out-of-Order (OoO) and SiFive-style cores. Mirabilis Design has a collaboration with Andes to support their suite of RISC-V processors. Please check on the latest list with Mirabilis Design.

VisualSim is at the forefront of RISC-V design and application deployment. It not only enables engineers to build and validate RISC-V processors but also to evaluate how RISC-V cores perform across diverse application domains such as automotive, AI/ML accelerators, IoT, HPC, networking, and aerospace.

Critically, VisualSim supports the import of Spike ISS traces, enabling engineers to run real software binaries on the RISC-V model. This ensures that workloads, drivers, and operating systems can be validated before silicon is available.

Overview

Supported Standards

Key Parameters

  • Processor_Speed_MHz – Clock rate of the RISC-V core.
  • Processor_Name – Type of RISC-V core (In-Order, OoO, SiFive).
  • Pipeline_Stages – Depth of pipeline.
  • Number_of_Registers – Configurable register file size.

Parameter Snapshots

  • Parameter

Simulation Results

  • Instruction Throughput – IPC, stalls, hazards.
  • Cache Behavior – Hit/miss ratios across workloads.
  • Energy Efficiency Reports – Power vs. performance trade-offs.
  • Software Validation – Spike ISS trace execution analysis.
  • Plot 1
  • Plot 2

Application

  • Automotive – Domain controllers and RISC-V-based ECUs.
  • AI & ML – RISC-V accelerators integrated with NPUs and GPUs.
  • IoT & Edge Devices – Low-power, 32-bit embedded RISC-V cores.
  • Networking & Telecom – Packet processing and secure gateways.
  • HPC & Data Centers – Out-of-Order, multi-core RISC-V for compute clusters.
  • Aerospace & Defense – Custom RISC-V cores for radiation-tolerant designs.

Integrations

  • Works with DDR, LPDDR, HBM, Flash, and NVMe controllers.
  • Connects to NoCs, PCIe, and CXL blocks.
  • Co-simulates with accelerators (GPU, DSP, FPGA, NPU) in heterogeneous SoCs.
  • Integrates into AUTOSAR, Linux, and RTOS environments for software testing.

View Demo

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