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Benefits

  • Faster NoC Construction: Build and validate in 1–2 days.
  • Cross-Vendor Flexibility: Supports ARM CoreLink, Arteris, Baya Systems, Signature IP, Cadence, and custom IP.
  • Early Bottleneck Detection: Identify congestion hotspots before RTL.
  • Arbitration Flexibility: Modify arbitration order to match different specifications.
  • System-Level Insight: Measure latency, throughput, and buffer utilization.
  • Reduced Risk: Optimize before silicon, avoiding costly redesigns.

The NoC (Network-on-Chip) Builder block in VisualSim enables engineers to rapidly design and validate custom interconnects for SoCs, AI accelerators, and heterogeneous multi-core systems.

Unlike manual design, which can take weeks or months, VisualSim’s NoC Builder allows a new NoC to be constructed in 1–2 days, significantly accelerating design iteration. Engineers can explore routing strategies, arbitration schemes, QoS settings, congestion behavior, and buffer sizing before committing to RTL or IP selection.

VisualSim supports both commercial NoCs such as ARM CoreLink and Arteris FlexNoC, as well as Baya Systems/Signature IP and Cadence interconnects, while remaining flexible enough to model in-house or custom-built NoCs.

How VisualSim Solves the Problem

The Problem

Modern SoCs face challenges in:

  • Scaling communication between dozens or hundreds of cores.
  • Managing bandwidth-hungry workloads (AI/ML, networking, multimedia).
  • Ensuring QoS for mixed-criticality traffic (safety, infotainment, control).
  • Handling latency, contention, and congestion hotspots.
  • Evaluating arbitration strategies and routing algorithms early in design.

The VisualSim Solution

The NoC Builder provides a drag-and-drop environment to create routers, interfaces, virtual channels, and arbitration policies with system-level visibility. It allows engineers to:

  • Build custom or commercial-style NoCs in days instead of weeks.
  • Simulate congestion, throughput, and latency under realistic workloads.
  • Validate QoS, fairness, and arbitration policies before hardware lock-in.
  • Analyze buffer utilization and flow control schemes for efficiency.
  • Compare different NoC topologies (mesh, ring, tree, hybrid).

Features That Enable This

  • Buffer Management & Flow Control – Ensures efficient data transfer.
  • QoS and Bandwidth Control – Configure arbitration and traffic priority.
  • Virtual Channels – Prevent head-of-line blocking and improve throughput.
  • Request & Reorder Buffers – Guarantee correctness and fairness in delivery.
  • Router & Interface Models – Parameterized to match commercial or in-house IP.
  • Scalability – Supports small embedded SoCs to large AI/HPC fabrics.

Key Parameters

  • Router_Speed_Mhz: Operating frequency.
  • No_Of_VC_Per_Port: Virtual channel configuration.
  • Bandwidth_per_Port_Mbps: Link throughput allocation.
  • Interface_Buffer_Size: Request/response buffering.
  • Flit_Size_Bytes: Granularity of packetized transfers.

Parameter Snapshots

  • Parameter 1
  • Parameter 2
  • Parameter 3
  • Parameter 4

Simulation Results

  • Congestion Analysis: Identify traffic hotspots and buffer overflows.
  • Latency & Throughput Reports: Measure end-to-end data transfer efficiency.
  • QoS Validation: Evaluate priority traffic performance under load.
  • Arbitration Studies: Compare fairness and throughput under different policies.
  • Plot 1
  • Plot 2
  • Plot 3
  • Plot 4

Applications

The NoC Builder is used across:

  • Semiconductors: AI/ML accelerators, networking ASICs, heterogeneous SoCs.
  • Automotive: Multi-ECU, ADAS, and autonomous vehicle platforms requiring predictable latency.
  • Aerospace & Defense: Mission-critical NoCs with redundancy and deterministic QoS.
  • Datacenter & HPC: Multi-core CPUs, GPUs, and memory subsystems with high bandwidth demand.
  • Custom In-House NoCs: Architecture teams designing proprietary fabrics.

Integrations

  • Connects seamlessly with: memory controllers (DDR, LPDDR, HBM, GDDR).
  • Works with: CPU, GPU, DSP, NPU, and accelerator models as masters/initiators.
  • Interfaces with: Gateways, Bridges, and Routers for hierarchical NoC design.
  • Supports: in-house extensions, enabling custom arbitration or routing logic.

View Demo

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