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Benefits

Using the HMC block in VisualSim provides:

  • Ultra-High Bandwidth: Packet-based transfers outperform DDR/GDDR in many scenarios.
  • Reduced Latency: Integrated logic layer shortens access times.
  • Scalable Interconnects: Multiple cubes connected through serial links.
  • System Reliability: Built-in error correction and retry mechanisms.
  • Power Efficiency: Energy per bit transfer lower than wide-bus DRAM.
  • Hybrid Exploration: Study trade-offs between HMC, HBM, and DDR in the same system.

The Hybrid Memory Cube (HMC) block in VisualSim models 3D-stacked memory with logic layer integration, designed to deliver extremely high bandwidth and low latency for advanced computing systems. Unlike DDR and GDDR, which use wide parallel interfaces, HMC employs a serial, packet-based interface that allows much higher throughput and simplified routing.

HMC technology was introduced in 2011 by Micron and Intel, with JEDEC attempting standardization as JESD235 (parallel to HBM). While HBM became the dominant standard, HMC pioneered many concepts — such as logic layers for intelligent memory management, packetized access, and scalable cube stacking — that influenced modern memory technologies.

Adoption was strongest in HPC, defense, and networking systems, with major users including Micron, Intel, Fujitsu, Cray, and IBM in supercomputers and high-end datacenter deployments.

The HMC block in VisualSim allows designers to explore multi-interface connectivity, routing logic, power monitoring, and latency analysis, enabling accurate studies of HMC-based and hybrid memory architectures.

Overview

The HMC block includes the following architectural elements:

  • Memory Controller: Manages high-speed data transfers to/from memory cubes.
  • Multiple Memory Interfaces: Allows connection of different memory sources simultaneously.
  • Switching Logic: Routes transactions between source and destination devices.
  • Packet-Based Interconnect: Serial, scalable links replacing wide bus architectures.
  • Latency & Power Monitors: Tracks efficiency and energy trade-offs.
  • Multi-Host Support: Connects multiple processors to multiple memory controllers.
  • Stacked DRAM Layers + Logic Layer: 3D stacking with integrated control and routing logic.

Supported Standards

HMC is aligned with:

  • Hybrid Memory Cube Consortium (2011): Founded by Micron, Samsung, ARM, and Microsoft.
  • JEDEC JESD235 Drafts: Early standardization effort, later diverged into HBM adoption.
  • Serial Interface Protocols: Inspired by PCIe-like packet protocols for scalability.

Key Parameters

Key configurable parameters include:

  • Mem_Controller_Speed: Operating speed of the memory controller.
  • Mem_or_Src: Defines source memory type connected to HMC.
  • Destination_Devices: Target processors/memory controllers.
  • Interface_Count: Number of independent HMC links.
  • Stack_Size: Number of DRAM layers per cube.
  • Power_Monitor_Enable: Enables energy consumption tracking.
  • Error_Correction_Mode: Configurable ECC support.

Parameter Snapshots

  • HMC
  • HMC Switch

Simulation Results

  • Latency Reports: Access times across serial HMC links.
  • Bandwidth Analysis: Sustained vs. peak throughput comparisons.
  • Power Studies: Energy per transfer vs. DDR/HBM.
  • Topology Reports: Performance with multi-host, multi-cube connectivity.
  • Latency
  • Stats

Application

HMC has been deployed in specialized high-performance domains:

  • AI & Machine Learning:
    • Early accelerators for matrix/tensor workloads.
    • Research systems requiring ultra-low latency.
  • High-Performance Computing (HPC):
    • Cray XC and IBM supercomputers.
    • Exascale research prototypes.
  • Networking & Telecom:
    • Routers and switches requiring high buffer throughput.
    • Real-time analytics in 5G/edge infrastructure.
  • Aerospace & Defense:
    • Mission-critical, radiation-tolerant computing.
    • Secure HPC for military simulation.
  • Datacenters:
    • Used in experimental FPGA and accelerator platforms for data-intensive workloads.

Integrations

  • Works with processors, GPUs, and FPGA models to test heterogeneous architectures.
  • Integrates with AXI, CoreLink, and Arteris interconnects for system-level modeling.
  • Can be combined with HBM and DDR blocks to compare or simulate hybrid memory hierarchies.
  • Supports multi-host / multi-memory system design exploration.

View Demo

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