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Benefits

Using the Flash block in VisualSim provides:

  • Accurate Performance Modeling: Simulates sequential/random reads and write latencies.
  • Reliability Testing: Models erase cycles and error scenarios.
  • Design Flexibility: Supports multiple page/block size configurations.
  • System-Level Integration: Evaluate flash performance within complete SoC/storage subsystems.
  • Power Optimization: Explore effects of access frequency and low-power modes.
  • Trade-off Studies: Compare NOR vs. NAND behavior for different workloads.

The Flash block in VisualSim represents non-volatile flash memory used for read, write, and erase operations. Unlike volatile memory (such as DRAM), flash retains data even when power is removed, making it ideal for long-term storage and firmware applications. Flash can be integrated with NVMExpress and other standards. Also, you can instantiate multiple flash in a single model. The flash can be controlled by external processors to create a SSD.

Flash memory technology emerged in the 1980s, pioneered by Toshiba (NAND flash, 1987) and Intel (NOR flash, 1988). It quickly replaced EEPROM in many applications due to its higher density, lower cost, and faster erase/write cycles.

Today, flash is ubiquitous across industries. Samsung, Micron, Kioxia, SK Hynix, and Western Digital are the leading manufacturers. Flash is widely used in consumer electronics (smartphones, USB drives, SSDs), automotive systems (ECUs, infotainment), and datacenter storage (NVMe SSDs, all-flash arrays).

The Flash block in VisualSim allows engineers to simulate sequential/random reads, fast writes, erase cycles, and page-level configurations, enabling accurate studies of latency, endurance, and storage efficiency.

Overview

The Flash block includes key functional features:

  • Read & Write Operations: Supports both sequential and random reads, plus write access.
  • Erase Function: Models erase-before-write operations at block level.
  • Bus Interface: Connects flash to system buses for data transfer.
  • Page Size Configuration: Defines memory block/page sizes for efficient storage management.
  • Timing Parameters: Separate sequential vs. random read timings for realistic performance.
  • Wear Modeling (optional): Models program/erase (P/E) cycle endurance and degradation.
  • Error Models: Can simulate bit errors for reliability studies.

Supported Standards

Although flash technology itself is not governed by a single universal standard, it aligns with JEDEC standards for NAND/NOR flash:

  • NAND Flash (SLC, MLC, TLC, QLC): High-density storage for SSDs and mobile.
  • NOR Flash: Fast random reads for boot and embedded firmware.
  • ONFi (Open NAND Flash Interface): Defines electrical and protocol-level interfaces.
  • NVMe over Flash (via SSDs): Standardized flash access in datacenters.

Key Parameters

Configurable parameters include:

  • Sequence_Read_Time: Latency for sequential reads.
  • Random_Read_Time: Latency for random reads.
  • Write_Access: Write latency and throughput.
  • Page_Size: Configurable block/page size.
  • Bus_Speed: Interface speed to connected bus.
  • Erase_Cycle_Time: Time to erase a block before rewriting.
  • Endurance_Limit: Number of program/erase cycles before degradation.
  • Error_Rate: Probability of bit error in long-term operation.

Parameter Snapshots

  • Parameter

Simulation Results

  • Plot
  • Stats

Application

Flash memory is a cornerstone of modern storage systems. The Flash block is applicable to:

  • Consumer Devices: USB drives, smartphones, tablets, cameras.
  • Datacenters: SSDs and NVMe arrays for high-performance workloads.
  • Automotive Systems: Boot memory, ECU logging, and infotainment.
  • IoT & Embedded Systems: Low-power, non-volatile storage for firmware and data logs.
  • Industrial Automation: Ruggedized flash for PLCs and real-time systems.
  • Medical Devices: Imaging, diagnostics, and secure logging.

Integrations

  • Works with processor, cache, and memory controller blocks for full memory hierarchy modeling.
  • Integrates with bus models (AXI, PCIe, CoreLink, Arteris NoC).
  • Can be combined with storage controllers (NVMe, SSD models) for end-to-end I/O studies.
  • Supports cross-domain use cases, including networking, automotive, and embedded systems.

View Demo

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