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Benefits

Using the CoreLink block in VisualSim provides clear advantages:

  • Early Performance Evaluation: Analyze data flow, latency, and congestion at the system level.
  • Scalability: Model interconnects from small SoCs to multi-die chiplet systems.
  • Protocol Flexibility: Support for AXI, CHI, ACE, and other interconnect standards.
  • Traffic-Aware Analysis: Evaluate workloads such as AI inference, video processing, and networking.
  • Design Trade-offs: Compare different routing policies and topologies (crossbar, mesh, tree).
  • Bottleneck Detection: Identify underutilized links or oversubscribed paths early.

The CoreLink block in VisualSim models high-performance interconnect IP that connects processors, accelerators, memory controllers, and peripherals within a System-on-Chip (SoC). Acting as the backbone of the SoC, it provides low-latency, high-bandwidth communication, ensuring that data moves efficiently between heterogeneous components. This library covers the CMN600, CMN700, CMN-Cyprus and the upcoming CMN standards.

Using CoreLink in VisualSim, designers can explore system topology, routing, bandwidth allocation, and latency behavior under different workloads. This allows architects to evaluate how data flows, identify bottlenecks, and make informed trade-offs in early design phases before implementation.

The CoreLink block in VisualSim models the full range of CoreLink components, enabling accurate simulation of system-level interconnect behavior. Supported elements include:

RN-F (Request Node – Full): Interfaces CPUs and accelerators with the coherent interconnect.

RN-I (Request Node – I/O): Connects I/O masters to the interconnect.

RN-S (Request Node – System Cache): Provides system-level cache access points.

HN-F (Home Node – Full): Manages cache coherency and memory access for attached slaves.

HN-I (Home Node – I/O): Handles I/O coherence and memory transactions.

HN-S (Home Node – System Cache): Provides shared cache management.

XP (Crosspoints): Route data across the interconnect and manage traffic flow.

CMN Routers (Switches): Form the backbone of the CoreLink mesh interconnect.

SLC (System Level Cache): Shared caching layer for latency reduction and bandwidth optimization.

Memory Interfaces: DDR/LPDDR/DRAM connections for off-chip access.

Peripheral Bridges: Linking legacy buses or custom components to the interconnect.

Additional functionality includes:

Temporary Buffering: Handles traffic bursts and reduces queuing delays.

Protocol Compatibility: Supports AXI, CHI, and ACE protocols across devices.

Routing & Mapping: Directs data via configurable static routing tables and address maps.

Performance Monitoring: Collects statistics on latency, bandwidth, congestion, and QoS.

Overview

  • Facilitates fast communication between processors, accelerators, memory, and I/O peripherals.
  • Provides temporary buffering to manage traffic bursts and minimize delays.
  • Supports protocol compatibility across heterogeneous subsystems.
  • Implements routing policies to direct data to the correct destination.
  • Tracks latency, throughput, and congestion metrics for performance analysis.
  • Allows static routing table and system address mapping to configure data paths.

Supported Standards

While not bound to one specific standard, the CoreLink block aligns with widely used industry interconnect protocols:

  • AMBA AXI4/AXI5 for high-performance bus-based communication.
  • AMBA CHI (Coherent Hub Interface): For cache-coherent multi-core SoCs.
  • ACE / ACE-Lite: Coherency extensions to AXI.
  • AXI-Stream: For high-bandwidth, streaming data transfer.
  • TileLink: Open-source coherent interconnect support.
  • UCIe, PCIe and CXL: For high-speed die-to-die, chiplet interconnect, and interfaces.

Key Parameters

Key configurable parameters include:

  • Static Routing Table: Defines fixed data paths between initiators and targets.
  • System Address Map: Maps memory and peripheral addresses to interconnect destinations.
  • Link Bandwidth (GB/s): Determines throughput per path.
  • Latency Settings: Base latency plus per-hop delay modeling.
  • Buffer Depths: Configurable FIFO sizes for traffic management.
  • Arbitration Policies: Round-robin, priority-based, or weighted schemes.
  • QoS Controls: Assign bandwidth and latency priorities to critical traffic.
  • Power Estimation: Energy consumed per transfer for PPA analysis.

Parameter Snapshots

  • CMN600 Setup
  • Router XP

Simulation Results

  • Latency & Bandwidth Reports: Detailed measurements of traffic delays and throughput.
  • Utilization Analysis: Tracks interconnect resource usage across workloads.
  • Routing Studies: Impact of static routing and address map policies.
  • Congestion Maps: Identify oversubscribed links and hotspots.
  • Scalability Reports: System performance as node count increases.
  • Max Network Latency
  • Max End to End Latency
  • Latency

Applications

The CoreLink block is applied across a wide range of heterogeneous SoC designs:

  • Mobile & Consumer SoCs: Connecting CPUs, GPUs, NPUs, and memory controllers for smartphones and tablets.
  • Automotive Systems: Supporting ADAS, infotainment, and real-time control workloads.
  • AI/ML Accelerators: Handling high-bandwidth data transfers between tensor engines and memory.
  • Datacenter & HPC SoCs: Enabling scalable memory and compute interconnects.
  • Networking & 5G SoCs: Efficient packet handling and QoS management.
  • Aerospace & Defense: Providing reliable, deterministic interconnects in safety-critical applications.

Integrations

  • Works seamlessly with processors, caches, accelerators, and memory models in VisualSim.
  • Can integrate with NoC (Network-on-Chip) models such as Arteris FlexNoC.
  • Supports integration with chiplet-level interconnects (UCIe, CXL) for heterogeneous systems.
  • Enables co-simulation with external traffic generators for stress testing.

View Demo

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