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Benefits

Using the Arteris NoC block in VisualSim provides measurable advantages:

  • Early Validation: Identify bottlenecks before RTL implementation, reducing risk of re-spins.
  • Performance Analysis: Measure end-to-end latency, throughput, and link utilization.
  • QoS Control: Ensure bandwidth and priority for safety-critical and real-time data streams.
  • Scalability: From small SoCs to chiplet-based AI/Datacenter platforms.
  • Power & Thermal Awareness: Model NoC energy consumption to support PPA trade-offs.
  • Failure Analysis: Simulate fault conditions, retry mechanisms, and deadlock scenarios.

The Arteris NoC (Network-on-Chip) library package in VisualSim models a scalable and performance-optimized interconnect for SoCs. It supports communication between CPUs, GPUs, accelerators, memory, and I/O, replacing traditional bus-based designs with modular and hierarchical topologies. Designers can simulate latency, bandwidth, congestion, and QoS enforcement early in the design phase, enabling informed trade-off decisions before RTL or physical design. The library contains FlexNoC and NCore. The library components support the entire suite of NIU, Switches, MUX, DEMUx, Memory Schedulers and a host of other devices. The library includes both static and adaptive routing, seven types of arbitration, multi-level scheduling and Virtual Channels. The purpose of the Arteris NoC library is for a designer to experiment with different topologies, placement of cores, cache, interfaces, DMA and memories, sizing of the buffers, selection of arbitration schemes, and clock speed selection. Over 20 different statistics are generated for each building block inluding efficiency, latency, throughput, buffer occupancy, power consumption and bottlenecks. The output of this model can be fed into the ARteris design tool for the generation of RTL and placement information.

Key features include parallel data stream support, deadlock avoidance mechanisms, and resource utilization analysis for complex architectures like AI accelerators, automotive SoCs, and chiplet-based systems.

The library consists of Initiator NIU, Target NIU, Switch, Mux, Demux, Memory Scheduler, UCIe connector and other interfaces. The Noc NIU can conenct to the complete suite of VisualSim masters and slaves such as processors and memories.

VisualSim models referencing vendors are independent abstractions developed and validated using publicly available architectural and software information, are not endorsed by the original owner, and all trademarks and product names remain the exclusive property of their respective owners.

Overview

The Arteris NoC block in VisualSim models all the building blocks of Arteris FlexNoC® and Ncore® interconnect architectures, enabling complete system-level exploration. Supported devices include:

  • Network Interfaces (NIUs): Connect initiators (CPUs, GPUs, accelerators, DMA) and targets (memory controllers, peripherals) to the NoC.
  • Routers/Switches: Route packets (flits) through the interconnect fabric.
  • Virtual Channels (VCs): Provide parallel logical paths for QoS and deadlock avoidance.
  • Arbitration Units: Manage access priorities for competing flows.
  • Buffers (Ingress/Egress): Temporary storage to handle congestion and burst traffic.
  • Traffic Shapers: Enforce bandwidth allocation and latency constraints.
  • QoS Controllers: Guarantee priority for safety-critical or high-bandwidth streams.
  • Protocol Converters: Support heterogeneous traffic (AXI, CHI, OCP, TileLink, etc.).
  • Coherency Managers (for Ncore®): Manage cache-coherent communication across clusters.
  • Debug & Performance Monitors: Capture latency, throughput, congestion, and error metrics.

Additional functionality includes:

  • Topology Options: Mesh, torus, ring, tree, hierarchical, or custom NoC layouts.
  • Deadlock Avoidance Mechanisms: Virtual channels and ordered transaction handling.
  • Link Bandwidth & Latency Controls: Define performance for each connection.
  • Scalability: From small embedded SoCs to multi-die chiplet interconnects.
  • Manage data routing between different nodes in the NoC.
  • Facilitate efficient data transfer between multiple interconnected components.
  • Support multiple communication streams to prevent data congestion.
  • Ensure prioritized data transfer for critical tasks.
  • Track latency, throughput, and congestion across the NoC.

Supported Standards

The Arteris NoC block supports both proprietary and open industry standards for interconnect protocols:

  • Arteris Proprietary: FlexNoC®, Ncore®, FlexWay®
  • Integration with AMBA: AXI4, AXI5, ACE (for cache coherency)
  • OCP (Open Core Protocol)
  • CHI (Coherent Hub Interface)
  • TileLink
  • CCIX (Cache Coherent Interconnect for Accelerators)
  • CXL (Compute Express Link) – accelerator/memory interoperability

Key Parameters

Key simulation and modeling parameters include:

  • Topology: Mesh, torus, ring, tree, hierarchical, or custom topologies
  • Flit Size: Defines data packet granularity
  • NoC Clock Frequency / Router Speed
  • Buffer Depths: Input and output buffer sizing for congestion management
  • Virtual Channels: Configurable per-router to avoid deadlock and enable QoS
  • Link Bandwidth (Gbps)
  • Arbitration Policy: Round-robin, weighted, or priority-based
  • Power Models: Dynamic and leakage power per transfer
  • Traffic Patterns: Random, hotspot, uniform, application-specific
  • Error Handling: Parity, ECC, retry mechanisms

Applications

The Arteris NoC block in VisualSim is used to **simulate, validate, and optimize interconnect architectures** in complex SoCs:

  • AI/ML Accelerators: Managing high-bandwidth data transfer between compute cores and memory.
  • Automotive SoCs: Guaranteeing QoS and low latency for ADAS and infotainment systems.
  • 5G & Networking: Supporting deterministic throughput for packet processing and signal paths.
  • Aerospace & Defense: Ensuring reliability and fault tolerance in mission-critical environments.
  • Chiplets & Heterogeneous Integration: Validating die-to-die communication using UCIe, CXL, or proprietary interconnects
  • HPC Systems: Reducing bottlenecks in massively parallel compute workloads.

Integrations

  • Compatible with VisualSim’s processor, memory, and accelerator models, enabling full system-level simulation.
  • Can be combined with third-party traffic generators and protocol checkers for validation.
  • Supports integration with chiplet modeling frameworks for multi-die system exploration.

View Demo

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