In formal terms, a directed graph is an ordered pair G = (V, A) where • V is a set whose elements are called vertices, nodes, or points; • A is a set of ordered pairs of vertices, called arrows, directed edges (sometimes simply edges with the corresponding set named E  instead of A), directed arcs, or directed lines.  It differs from an ordinary or undirected graph, in that the latter is defined in terms of unordered pairs of vertices, which are usually called edges, […]

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Reachability and DAG Reduction Example: The reachability relationship in any directed acyclic graph can be formalized as a partial order ≤ on the vertices of the DAG. In this partial order, two vertices u and v are ordered as u ≤ v exactly when there exists a directed path from u to v in the DAG; that is, when v is reachable from u.  However, different DAGs may give rise to the same reachability relation and the same partial order.  For example, the […]

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Configurable TDP: Configurable TDP (cTDP), also known as programmable TDP or TDP power cap, is an operating mode of later generations of Intel mobile processors, as of January 2014, and AMD processors, as of June 2012, that allows adjustments to their TDP values. By modifying the processor behavior and its performance levels, power consumption of a processor can be changed by altering its TDP at the […]

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DAG One Way Example; note no return to prior state a,b,c,d: A graph is formed by vertices and by edges connecting pairs of vertices, where the vertices can be any kind of object that is connected in pairs by edges. In the case of a directed graph, each edge has an orientation, from one vertex to another vertex. A path in a directed graph is a sequence of […]

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Power consumption can be reduced in several ways, including the following: • Voltage reduction –  dual-voltage CPUs, dynamic voltage scaling, under-voltage, etc. • Frequency reduction –  under-clocking, dynamic frequency-scaling, etc. • Capacitance reduction – increasingly integrated circuits that replace PCB traces between two chips with relatively lower-capacitance on-chip metal interconnect between two sections of a single integrated chip; low-k dielectric, etc. • Power gating techniques such as clock […]

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