ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe

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ARM CoreLink, Arteris NoC, UCIe, Bunch-of-Wires, CXL, and PCIe – Designing the Interconnect is Not for the Weak-Hearted!

In today’s high-stakes world of System-on-Chip (SoC) design, figuring out the best interconnect architecture can feel like navigating a maze. With so many choices—ARM CoreLink CMN700, Arteris FlexNoC, UCIe, Bunch-of-Wires, CXL, and PCIe—it’s easy to feel overwhelmed.

That’s why Mirabilis Design is hosting a webinar to help clear the confusion. We’ll walk you through how system modeling can help you make sense of it all by giving you the hard data you need to make the right choices.

Why You Should Attend

If you’re working as a SoC architect, power architect, systems engineer, or product manager, this webinar is for you.

We know what keeps you up at night:

  • Is ARM CoreLink CMN700 or Arteris FlexNoC the better fit for your project?
  • Where do PCIe and CXL fit in the bigger picture?
  • And when it comes to chiplets, should you go with UCIe or Bunch-of-Wires?

These aren’t easy questions, especially as AI workloads and heterogeneous computing become more common. But don’t worry—we’re here to show you how system modeling can take the guesswork out of these decisions.

What You’ll Learn

We’ll use real-world examples, like mapping a CNN (ResNet-50) onto an AI processor, developing an Open Architecture Management (OAM) system, and building a custom NoC for a heterogeneous SoC with FPGA, to show you:

  • Key Metrics: Learn how to measure latency, throughput, buffer occupancy, power consumption, heat, cache performance, and memory bandwidth.
  • Testing & Validation: See how running standard and synthetic workloads can help you fine-tune your designs.
  • Troubleshooting Bottlenecks: Find out how to identify and solve bottlenecks by experimenting with different routing schemes, buffer sizes, flow control mechanisms, and more.

By the end of the webinar, you’ll have a better understanding of how to optimize your SoC or chiplet designs for performance, efficiency, and scalability.

Ready to Elevate Your SoC Design?

Don’t miss this chance to gain valuable insights and level up your SoC design skills.

Date & Time: 15th October 2024

  • Session 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China
  • Session 2: 10:00 AM USA PDT / 1:00 PM USA EDT

Register Now: https://www.mirabilisdesign.com/webinar-15oct/

We can’t wait to see you there!