ARM AMBA CHI5

AMBA 5 CHI network provides high-frequency, non-blocking data

AMBA Interface

  • ARM AMBA AHB/APB
    Advanced high performance bus (AHB) and AMBA advanced peripheral bus (APB) to connect with processors and IP
  • ARM AMBA AHB Bus Matrix
    AMBA-AHB Multilayer Bus matrix with self-Motivated Arbitration scheme
  • ARM AMBA AXI/ACP
    AMBA Advanced eXtensible Interface (AXI) point-to-point Bus
  • ARM AMBA CoreLink CMN-600
    CoreLink CMN-600 Coherent Mesh Network has been designed for extremely high data transfer
  • ARM AMBA CHI5
    AMBA 5 CHI network provides high-frequency, non-blocking data

Quick Explanation

  • Supports coherent interconnects
  • Supports Quality of Service
  • Support priority and credit
  • Support RN-F, RN-I, HN-F, HN-I and SN-F
  • Support DMA and bridges
  • Supports up to 8 DDR4 DRAM interface
  • Integrated with AXI buses for compatitbility with older IP blocks

Protocol

  • Arm AMBA CHI5

AMBA 5 CHI

AMBA 5 CHI is targeting the interface to the coherent hub that is found in many of today’s SoCs, hence the name “Coherent Hub Interface”. Back in the early days of on-chip coherency, it wasn’t all that clear about how much support would be needed for coherency and how widely adopted it would become within any given SoC. It was always clear that there would be a few key components that would need to have fully coherent caches, but whether that would spread far across the SoC was less clear. The landscape today is that coherency is being more broadly adopted. The trend in the enterprise today is more about an increasing number of coherent CPUs rather than a whole scale adoption of full coherency by all the processing engines within the SoC.

The AMBA 5 CHI (Coherent Hub Interface) architecture specification defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance, non-blocking interconnects such as the CoreLink CMN-600. It is appropriate for a wide range of applications that require coherency including mobile, networking, automotive and data centre.

The CHI specification separates the protocol and transport layers to allow different implementations to provide the optimal trade-off between performance, power and area. This separation allows interconnecting designs ranging from an efficient, small cross-bar to high performance, large scale mesh network.

CHI has been architected to maintain performance as the number of components and quantity of traffic rises.  This includes placing additional requirements on masters to respond to coherent snoop transactions, which means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.

The protocol also provides a Quality of Service (QoS) mechanism to control how resources in the system shared by many processors are allocated without needing a detailed understanding of every component and how they might interact.

Standards

The CHI architecture provides a comprehensive layered specification to build small, medium, and large systems comprising of multiple components using a scalable coherent hub interface and on-chip interconnect. The CHIarchitecture permits flexibility on the topology of the component connections, which can be driven from the system performance, power, and area requirements.

The CHI coherence protocol supports

  • Coherency granule of the 64-byte cache line
  • Snoop filter and directory-based systems for snoop scaling
  • Additional partial and empty cache line states

Component Naming

RN –  Request Node. Generates protocol transactions, including reads and writes to the interconnect.

HN – Home Node. Node located within the interconnect that receives protocol transactions from RNs.

The transaction types presented in this model are:

  • Request transactions without a Retry.
  • Request transactions with a Retry.
  • Snoop transactions

Model Explanation

There is an RN-F which is the Interface block in front of the Source.  The Source will most likely be the L3 Cache connected to the processor core. There can be multiple RN-F and Memory controllers connected to the network.  These are connected to the Device Ports of the router.

There are multiple Home Controllers associated with each Memory Controller.  Each Home Controller maintains a range of shared memory addresses. Each Home Controller can have an address listed associated with a single Memory controller.  They cannot have a list of addresses that traverse across multiple memory controllers. The list of Shared Addresses and associated Home Controller is stored at the top-level Database blocks.

Access_Database: Each Home Controller will have a Database block with a list of Addresses and the Devices that have made Read or Write requests. The Read and Write request will be Arrays.

When a Read request is sent from the Cache to the bus output, If it is not shared it is sent to the memory directly. If the address is one of the Shared Addresses, it will send it to the appropriate Home Controller.  The Home controller will do a lookup on the local Access_Database and check if anyone has made a written request to this address. If there are none, it sends the read request to the memory controller.  The memory will send the data back directly to the Cache.

If someone has made a written request and an Ack has not been received, it will send a message to the respective list of Caches and ask to Write to Memory.  If the Cache has already written it to memory, it will send an Ack back to the Home Controller.  If it has not written it, then it will write. After it has written it will send an Ack message to the Home controller.

When the Device has written the current data to the memory, the device is removed from the Access_Date. At this point, the Home Controller will send the Original Read request to the memory.  The memory will respond back directly to the Cache.

When a Write request is sent out from the Cache to the Memory, If it is not a shared address, then the writer will be sent to the Memory. If it a shared address, the write request is sent to the Memory.  After the data has been written to memory, an Ack is sent to the Home Controller. The Home Controller updates the database.

At this point, the Home controller will send a message to all those Caches that requested a read from this address.  This is the ReRead.  All those that still have the address in their cache will initiate a read. When they are done, they will send an Ack back to the Home Controller.  If they no longer have that address in their cache, they will send a Nack to the Home controller. The Home controller will remove that read requesting device from that address.