A7

power-performance model

Quick Explanation

  • Support for Big.Little architecture
  • Supports two-level cache execution units
  • Supports multiple levels of memory Partial dual-issue, in-order microarchitecture 8-stage pipeline NEON SIMD instruction set extension VFPv4 Floating Point Unit Thumb-2 instruction set encoding
  • Typical Clock Speed 400MHz to 1.5GHz

Protocol

  • ARM Cortex-A7 MPCore is a 32-bit microprocessor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2011

Implements Advanced Encryption Standard instruction set on dual ARM 7 platform