Quick Explanation
- Supports ARM V8 ISA
- Provides the NpBench's networking task profile, for benchmarking purposes
- Superscalar processor, capable of dual-issuing some instructions
- Integration with A72 for big.LITTLE configuration
- 8-stage pipeline
- 2-way superscalar
- In-order execution pipeline
- DSP and NEON SIMD extensions provided per core
- VFPv4 Floating Point Unit onboard (per core)
- 64-byte cache lines
- 10-entry L1 TLB, and 512-entry L2 TLB
- Supports generation of mispredict and pipeline flush
Protocol
- ARM Cortex-A53 implements the ARMv8-A 64-bit instruction set
