VisualSim – Power Solution

admin_mirabilis

VisualSim - Power Solution

VisualSim offers Power Solution starting from power generation to power distribution. There is also a support for Power Verification. The architects can make decisions such as allocation of power budget, selection or fine tuning the power management algorithms, sizing of power generators based on the observed results. Integration of Thermal Management allows the Architects to identify power spikes which can cause an increase in the surface temperature beyond the permissible threshold. 

These features are represented in the diagram below. 

Figure 1: VisualSim Integrated Power solution
Figure 1: VisualSim Integrated Power solution

Power Generation:

Figure 2 : Power Generators in VisualSim
Figure 2 : Power Generators in VisualSim

Time Based or Motor Based Power Generation is supported in VisualSim as shown in the figure above. 

The Power can be generated at a constant or variable charge capacity.

Power Storage: 

Battery Block allows the user to emulate the Power Storage Units. Results and statistics that can be obtained are shown below.

Figure 3 : Battery Block and the associated statistics
Figure 3 : Battery Block and the associated statistics

Power Consumption and Management: 

The user can configure a PowerTable with state based power allocation for the IP blocks in the system. 

Power States can also be defined using a state table.

The results that can be obtained are Instantaneous, Average and Cumulative power numbers:
The results that can be obtained are Instantaneous, Average and Cumulative power numbers:
Figure 4 : Power Manager and the results that can be obtained

Thermal Management :

The surface temperature and heat statistics that can be obtained based on the power state and instantaneous power changes are shown below.

Figure 5 : Thermal Management and the generated statistics

Debugging and downstream Integration: 

The PowerTable generates a StateChange output which can be recorded in a log file to debug the unexpected power numbers or to calculate the Power Consumption due to transition between the states. This will help the architect make informed decisions on how often they should be switching the block states in order to conserve power. 

 

The figure below shows an example of the power log file :

Figure 6 : PowerState change log file generated by the third port of PowerTable

For the downstream integration into RTL environment, a high level UPF format is generated. This UPF can be further refined as the design cycle progresses and more details are added to the design. 

The figure below shows an example of the UPF file showing the power domains and corresponding voltages assigned to them.

Figure 7: UPF Output 

The tool also converts the state transitions for a given model and the workload into a systemVerilog testbench which can be integrated into the RTL verification environments. The testbench dumps a VCD output when executed in any of the commercial or open-source EDA tools with system Verilog support.

Figure 8 : VCD dump from an open source EDA tool – obtained form the systemVerilof testbench generated in VisualSim