Memory

Controller delay, signal and address -based DRAM, SRAM and NAND

Cache, Memory and Storage

  • Cache
    Stochastic and cycle-accurate cache with snoop
  • Memory
    Controller delay, signal and address-based DRAM, SRAM and NAND
  • Disk
    Hard disk drive and hybrid drives with ARM and drive zone
  • Flash
    NAND memory with controller
  • SSD
    SSD connected to NVMe

Quick Explanation

  • Support read, write, prefetch and erase
  • Supports refresh
  • Memory signal timings
  • Separation of controller and DRAM
  • Enable user to integrate their own controller algorithm
  • Interface to PCIe, AMBA and FPGA
  • Support for proprietary Crossbar, switch, bus, NoC and other interfaces
  • Standard parameters for size, width, speed, buffer, commands in a row and thresholds
  • Standard activate, read and write signal timing

Protocol

  • SDR
  • DDR DRAM 1,2,3,4
  • RDRAM
  • SRAM
  • NAND

Model Link:

Overview

VisualSim has an extensive library of memories, caches and memory controllers to use in models based on Distributed Systems and System-on-Chip (SoC). The modelspossess an array of parameters that can be modified at the user’s discretion.They also provide a high-level of timing, throughput and power accuracy which will give extensive visibility into the internal operations of these components, thus allowing the designer to understand the possible bottlenecks or identify areas of improvement.

Standard Supported

  • Hierarchical cache with concurrent operations for high-level processor and SoC designing.
  • Memory modules such as SRAM, DRAM, and stochastic memory.
  • Widely used SDR, DDR, DDR2, DDR3, LPDDR, are some of the available presets within the model along with blocks such as Cycle-Accurate DRAM and Memory Controller

RAM

This block combines the operation of a basic Memory Controller and a Memory Array. It typically acts a storage device with the ability to simulate fetch, read, write, refresh and Control operations.

Features

  • Includes parameters such as Memory Speed, Memory Size, Memory Type, Access Time, and Refresh Cycles.
  • Supports standards such as SDR, DDR, DDR2, DDR3, etc.

Working and Usage

  • The memory receives request for data or instructions through its input ports. If multiple requests arrive, the memory can queue and process them on First Come First Served basis.
  • It is commonly interfaced with a Bus or a Memory Controller.
  • Almost every architectural model requires a RAM to complete its process.

Cycle-Accurate DRAM

This block emulates the common SDRAM technology and is used to capture the functionality and accurate timing of any variation of DRAM.

Features

  • Includes parameters such as DRAM Speed, Memory width, DRAM type, Number of banks, refresh rate, Simulation time.
  • Supports addressing, multiple banks, sequential, non-sequential, and random reads.

Working and Usage

Memory Controller

This block emulates the JESD 209 standard for LPDDR implementation..

Features

  • Includes parameters such as Controller Speed, Memory width, Bus width, DRAM type, Burst length, Simulation time.
  • It generates a timing diagram and plots read and write requests.

Memory-accesses DRAM if there is any misses in the internal memory and external cache