Architecture exploration, power and performance analysis early in the design flow are mandatory in modern SoC design flow due to complex multi-threaded applications and multi-core processing requirements. Instruction Set Simulator or ISS of a selected processor plays a very important role. However, Current Instruction Set Simulators (ISS) and platform modelers have detailed functional execution, tuned to verify an existing or selected platform. These require software to be available, detailed peripheral description and long simulation times. This also requires significant amount of time for integrating memory subsystem, interconnects, processor models and running application software itself.
This blog introduces a fast and accurate approach to constructing multi-core, multi-processor models for architecture trade-off, platform selection and processor design based on power and performance. The proposed approach is based on a statistical processor model that is customized using parameters from the vendor datasheet to describe a processor family with 80% accuracy. The parameters include internal device characteristics, pipeline stage descriptions and the instruction set. The resulting processor model has detailed pipeline activity interaction, interaction of instruction & data cache (Harvard Architecture) and internal instruction stream processing.
Accurate analysis of throughput, utilization, thread activity, stalls, hit-miss ration, pre-fetch, context cycles and state change has been generated and correlated with hardware. The processor model can generate power statistics using dynamic state change and management algorithms. Combining multiple processor instances and connecting to other configurable peripherals create a platform model. This technology is being incorporated in the VisualSim Processor Modeling Toolkit from Mirabilis Design.
The Processor Generator Toolkit enables users to generate detailed cycle-accurate simulation models of microprocessors, microcontrollers, DSP and application-specific processors in less than one day using only parameters. The toolkit enables processor architects to optimize the pipeline and instruction set, systems engineers to design new system platforms and software engineers to experiment with flows, thread distribution and scheduling long before an architecture commitment is made. The Processor Toolkit works by describing a processor using information from the vendor datasheet. This data is input into a wizard containing parameters, instruction table and pipeline stages. The resulting processor model is used to define complete systems with the Architecture Library components- RTOS, bus, switch, DRAM, DMA, controller and cache. Software instruction sequences and pseudo-code can be executed on this model for performance and power evaluations of multi-processor or multi-core systems. Some additional items that can be evaluated includes extensions for better pipeline to pipeline interaction across cores, memory-specific instruction and hardware threads.