Evaluate the software architecture and generate latency/throughput graphs
Most products are built using COTS or off-the-shelf parts. The design team must determine the right configuration to provide the hardware vendors. To arrive at the right configuration, the software architecture and the RTOS must be mapped onto the hardware platform and tested for the requirements. When embedded systems come into picture, there is very large scale system integration that needs to be done. For the proper execution of the model, a real time scenario may be tested, to see how feasible it is to implement it in real world. When multiple embedded systems are inter-connected using a network interface, the communication betweenthe software tasks has a large impact on real-time operation and meeting timing deadlines. The RTOS scheduling and interrupts activation is critical for proper operation and plays an important role in reliability and power management.
VisualSim Architect helps you build system architecture for future SoC, application-specific architectures based on embedded processors and requiring sophisticated hardware/software interfaces. The VisualSim Architect, models the software tasks that will be implemented in languages like C and C++, adds the overhead for the RTOS and any interrupts and communication.