Hardware-in-the-Loop

Interface to instruments and FPGA boards for connecting to data sources, hardware and software executing code

Hardware Devices

  • DMA
    Table-based customized DMA for use with and without a CPU
  • Bridge
    Parameter-based customized interface for use with 10 different protocols including PCIe and AXI
  • Switch/Crossbar/Serial Switch
    Backbone switch for use in SoC and systems
  • FPGA
    Multiple generations of Xiling FPGA including Virtex 4, Zynq 7000 and Ultrascale
  • Clock Tree
    Clock distribution to simulate jitters
  • UART
    Synchronous and asynchronous receiver-transmitter
  • Hardware-in-the-Loop
    Interface to instruments and FPGA boards for connecting to data sources, hardware and software executing code

1. VisualSim® Interface with Hardware or Hardware-in-the_loop

VisualSim modeling environment provides integration to instruments, hardware devices and FPGA in a Hardware-in-the-loop configuration. We have used VisualSim with Oracle Databases running on a remote servers, Xilinx Zynq 7000 platform board, remote instruments. However the source code and the setup is completely generic. This interface has been demonstrated on Xilinx Zynq 7000 platform board (Zybo board), using the Vivado tool suite fromXilinx and the accompanying Xilinx SDK. The version of Xilinx tool usedis Vivado 10.2. Using this interface the designer can communicate in both direction between VisualSim and the FPGA boards.

1.1 VisualSim FPGA Interface applications

VisualSim FPGA Interface can be used for System level analysis of Embedded Systems including performance, protocol checking, power, and for generating test scenarios for the target FPGA. VisualSim can generate verities of test scenarios very quickly and enables the user to validate application on FPGA covering all corner cases. VisualSim FPGA interface allows users to adopt below mentioned applications but it is not restricted.

  • Generating and running system level scenarios
    • VisualSim can be used to generate system level scenarios from the system definition.
    • Transferring the data to the FPGA to run actual datathrough the system.
    • Transfer the data back to VisualSim to perform analysis and display the information in user readable format.
  • Run performance simulations on the actual hardware system
    • VisualSim to generate complex use case scenarios that define performance bottle necks.
    • Run these scenarios on the actual hardware system.
    • Collect process and display the results, so system level optimizations can be performed.
  • Run power scenarios on the actual hardware
    • Generate complex power scenarios for the system.
    • Run these scenarios on the actual hardware.
    • Collect process and display the results, so system issues can be identified and fixed.