In each and every project, system engineers and hardware/software architects face the issues like correlation between a system level model and RTL, striving to achieve fidelity in system level model and the accuracy of the actual implementation.
The actual problem lies not in implementation, but on how to assemble the models. In this blog, we will discuss about the methodology enables the designers to create a design which incorporates all the checks and balances for successful implementation.
This step-by-step approach will ensure the management of the design flow:
- Build a baseline model: The model must be based on already available information and it could be the current system. It must be validated using the results of the current system.
- Build IP blocks or small parts of a model: It is important to verify each block independently to ensure that they are correct by themselves.
- Assemble the model: Test for simple cases to make sure they are mathematically correct.
- RTL or Software Development: Compare each block to the system model to ensure that they match within an error window. If they do, then the design meets the requirements. If they are out-of-range, then inspect both models to determine the cause of the error and update accordingly.
- Reuse System model for verification: An important approach of reusing the system model for verification is not to run a simple co-simulation. The two models have been built for different purposes and their interface is never really compatible. It is normally far easier to review the model details and build a System Verilog/VHDL/Verilog test bench.
This approach enables the proper assemble of the model and helps in managing correlation and accuracy issues in the system level model implementation. If you think there is more to add to this approach, feel free to share it.