System engineers and hardware/software architects are always worried about the correlation between a system-level model and RTL. Also, can a system-level model achieve the fidelity and accuracy of the actual implementation.
We at Mirabilis Design, have evolved a methodology that allows the user to create a design flow that incorporates all the checks and balances for this.
The methodology is really about how the models are assembled, as opposed to how they are implemented. This step-by-step approach will ensure the management of the design flow.
1. Build a baseline model. This model must be based on information that is already available. It could be the current system. This must be validated using the results of the current system.
2. Build IP blocks or small parts of a model: You verify each block independently. This way you make sure they are correct by themselves.
3. Now assemble the model: Test for simple cases to make sure they are mathematically correct.
4. During RTL or Software Development: Compare each block to the system model. Make sure they match within a error window. If they do, then the design meets the requirements. If they are out-of-range, then inspect both models to determine the cause of the error and update accordingly.
5. Reuse System model for verification: An important approach of reusing the system model for verification is not to run a simple co-simulation. The two models have been built for different purposes and their interface are never really compatible. It is normally far easier to review the model details and build a System Verilog/VHDL/Verilog test bench.
In VisualSim, we provide the ability to generate the VCD and to generate detailed graphical/textual description for generating the verification test bench. A co-simulation for both hardware and software languages is provided to round up the solution.