With so many Network-on-Chip (NoC) solutions available—like ARM CoreLink CMN700, Arteris FlexNoC, open-source interconnects, and even custom-built solutions—knowing when and where to use each option can be overwhelming. Should you opt for a backplane or integrate them within domains? How do protocols like AMBA AXI, PCIe, or CXL factor into your design? And with chiplet architecture gaining traction, do you choose UCIe or Bunch-of-Wires? Critical decisions also include the placement of DRAM and task schedulers.

This webinar will demystify these architecture decisions by showing how system modeling can provide the necessary quantitative metrics to validate and optimize your choices. We’ll demonstrate this using examples such as mapping a CNN (ResNet-50) onto an AI processor, building an Open Architecture Management (OAM) system, designing a heterogeneous compute SoC with FPGA, and developing a custom NoC.

To evaluate design quality, we will run both standard and synthetic workloads, generating key metrics like latency, throughput, buffer occupancy, peak power, heat dissipation, cache hit-miss rates, and memory bandwidth. We’ll also identify bottlenecks and explore how different design configurations—such as routing schemes, schedulers, buffer sizes, clock speeds, flits, clock domains, flow control, and quality-of-service—can impact overall performance.

Join us to learn how system modeling can help you make informed, data-driven decisions for your next SoC or chiplet design.