We used VisualSim to optimize the processor architecture to achieve 800 TeraFLOPS in three months. Using VisualSim modeling templates, we achieved an 80% cost reduction for modeling compared with SystemC. Without VisualSim, the modeling would have required over 1.5 years of development effort.
Using VisualSim, we have accelerated our architectural design and validation process. The VisualSim library enabled rapid development of a high-level SOC model allowing architectural validation at an early stage of the SOC development process.
VisualSim enables us to quickly construct the architecture of our next-generation products and run feasibility tests to maximize the performance, understand the reliability, and lower power consumption. We can perform all these tests prior to the development of any SystemC, Verilog or software.