September 30, 2012

Solutions

Mirabilis Design’s model-driven solutions enables design to meet the requirements and flexible for future enhancements. VisualSim is extremely powerful, very easy-to-use and faster time-to-results. Using VisualSim, a number of products are designed in the systems engineering space.

For a broader approach, VisualSim solution has been categorized into four industry-based  application and they are:




What we do:

  • Optimize and validate the specification
  • Devise optimal architecture in hardware and software development
  • Test and product debug

Why Us:

  • Visualize the system operations, program flow, timing and power consumption very early in the design cycle without including the details of the control algorithm, DSP functions and exact hardware components
  • Construct use cases and share them with partners and customers without divulging the implementation details
  • Conduct stress tests such as traffic loading, fault injection and dynamic worst-case analysis prior to scheduling any new development
  • Combine Finite-State Machine (FSM), data flow and discrete-event in a single model and  capture the mathematical, processing flow and control details all in a single environment.
System Specification and Design

Design flow begins with system specification and design phase. A complete visual evaluation of the system operation as a combination of traffic input, behavioral system definition and sink is done. This solution augments tools such as MatLab/Simulink and UML/SysML by providing very early visibility into the full system operation without getting into the details of the algorithm and code-level implementation.

Design Engineering Tasks

  1. Concept Engineering: Validate system requirements, estimate project feasibility, predict system flows and traffic patterns
  2. Proposal: Determining system resource requirements
  3. Product Definition: Early System, hardware and software co-specification
  4. Validation: Determining system reliability for different fault injections
  5. Communication: Executable specification

Example Usage

  1. Command, Control and Navigation for Satellite launch vehicle
  2. In-car networks using Ethernet, FlexRay and CAN
  3. Industrial automation drives migration to FPGA
  4. ATM-based Base Station boards
  5. Multimedia SoC with Network-on-Chip
  6. Processor with Dual-core PowerPC
  7. Submarine inertial system
  8. Industrial wireless sensor network

Reports and Analysis from VisualSim

  1. Resource utilization, bandwidth usage, buffer size and schedule allocation
  2. Quality of Service (QoS) estimation
  3. Power consumption and usage
  4. System traffic load, end-to-end response times and throughput
  5. Data flow trace and device activity report

Recommended Configurations:

  • Baseline:
  • VisualSim Architect
  • Batch-mode Simulation
  • Post Processor
  • Script
  • Smart Resource

Optional Libraries:

  • Networking
  • Wireless
  • VisualSim Satellite Toolkit
  • Spacewire
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Hardware Design

Hardware design forms second phase, as the hardware models are built after optimizing and validating system specification. Further hardware design is refined by adding specific hardware implementation details (processor pipeline, functional cache, accelerators and bus arbiters), logic, and cycle-level timing to the hardware model. These refinements provide cycle-by-cycle and address-level evaluation of the system functionality, performance and power. VisualSim’s hardware designs use parameterized transaction-level models to identify queue depths, arbitration correctness, read/write latency and effective memory throughput. 

The device can be a board, set of boards, SoC, sub-system or an Intellectual Property (IP). This solution can graphically import C++/C/Java, SystemC modules to reuse existing hardware models.

Design Engineering Tasks

  1. Selecting and sizing accelerators, cores, memory, interconnect and IO devices
  2. Traffic patterns in migration to many- and multi-core embedded architectures
  3. Designing the arbitration, queuing, translation and queuing of interconnect topologies
  4. Designing cache hierarchy, memory controllers and storage
  5. Assertions to debug specification and implementation for functionality, power and timing.
  6. Generate test patterns and the expected timing results for testing the device or IP block.

Examples

  1. Interconnect: Custom arbitration, topology, FIFO sizing and flow control policies for Network-on-Chip, AXI, AHB, PCI, PCIe, Serial Rapid IO, CoreConnect, Crossbar and Custom
  2. Memory Controller: Arbiters, Look-ahead buffers and load balancers for DDR, DDR2, DDR3, LPDDR, LPDDR2 and SRAM
  3. Storage: Processor selection, client arbiter, flash sizing of Solid-State Drives, Hybrid Disk, Rotating Disk
  4. Processor: 16-core Tensilica based Network Processor, 84-core Graphic Processor Unit, Custom ray tracing processor with 800 Tera-flops, OMAP power reduction and dual-core PowerPC
  5. Data Routers: Distribute payload and
  6. Wireless SoC with Network-on-Chip
  7. Android-based appliance power reduction

Reports and Analysis

  1. Bottleneck identification: Buffer occupancy, and checkpoints monitoring
  2. Timing: Read and Write latency
  3. System loading: Throughput and device utilization
  4. Task Execution flow: Gantt charts with timing, addresses and banks accessed

Recommended Configurations:

Baseline:

  • VisualSim Architect
  • Batch-mode Simulation
  • Post Processor
  • Script
  • Smart Resource

Optional Libraries:

  • Hardware Core Architecture
  • Bus Switch Controller
  • VisualSim FPGA Modeling Toolkit
  • Standard Bus/Network
  • PCie
  • AMBA 3
  • Memory
  • Serial Rapid IO
  • Spacewire
  • Switch Ethernet
  • Cycle-accurate Cache

Interfaces:

  • SystemC
  • Verilog
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Software Validation

VisualSim’s software design and validation environment enable users to construct virtual simulation models of the hardware with the environment, setup fault injectors, establish probes and tracking devices, and load the software. This phase impacts the safety and reliability of the system.  This model-based software in the loop enables to identify the areas of faults in the embedded system code. With VisualSim, it is easy to create corner case scenarios, and identify customer sequences, errors in usage, hardware malfunction, and illegally modified data and schedules. This VisualSim model can be refined with the detailed behavior operation of the task, the scheduling schemes, the RTOS attributes and the software code. As software is highly flexible, the model can conduct stress to identify all possible faults that could occur in the field.

Design Engineering Tasks

  1. Establish tests for compliance to standards such as ISO26262
  2. Inject faults to test the diagnostic capture of incorrect operation
  3. Check whether the diagnostics are sufficient to identify illegal operations
  4. Selecting the best hardware platform to meet the software performance requirements
  5. Task partitioning on multi-core, GPU, and other architectures
  6. Software module to thread to task mapping
  7. Identify system bottlenecks and possible hardware accelerators to meet the timing deadlines
  8. Select scheduling algorithms and parameters for RTOS and virtual partitions
  9. Impact of specific hardware structures
  10. Tuning RTOS and device driver attributes based on data dependencies and parallelization
  11. Validate interactions across multi-layer network topologies for acknowledgements and interaction

Examples

  1. Autosar expiry point offsets selection for a set of Runnable tasks.
  2. ARINC 653 scheduler parameter tuning
  3. Custom instructions selection based on CPU utilization
  4. Identify task bottlenecks and partitioning software modules to cores and accelerators
  5. DSP software flow optimization for efficient memory access
  6. Migration of Radar and image processing code to many core- many processor architectures
  7. Rewrite embedded software code for power efficiency

Reports and Analysis

  1. Timing: Mean and worst-case execution time analysis, and deadline range
  2. Resource bottlenecks: cache coherency, bus arbitrations and interrupts
  3. Reliability: Watchdog operation accuracy, error checking efficiency and program flow correctness

Recommended Configurations:

Baseline:

  • VisualSim Architect
  • Batch-mode Simulation
  • Post Processor
  • Script
  • Smart Resource

Optional Libraries:

  • Networking
  • Wireless
  • Standard Bus/Network
  • Memory
  • Cycle-accurate Cache
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Power Exploration

VisualSim’s Power Exploration component monitors the power consumed in every step of the design flow- system, hardware and software. Power modeling and exploration is an overlay to any VisualSim model to derive strategies to conserve energy using system, SoC and software techniques. All standard modeling components contain power state information. The user defines the state power levels and the transition cycles between states in an Excel spreadsheet and associates it with the model. The power values are dynamic, based on the system activity, and can be for a part or the full system.

Design Engineering Tasks

  1. Trade-off different architecture to achieve the performance requirement for the lowest power
  2. Distribute components and Intellectual Property (IP) to different power domains within the SoC and system
  3. Selecting the power management control and scheduling algorithm

Examples

  1. Android-based appliance power reduction
  2. Modify memory access scheme of embedded software code for low-power
  3. Dynamic instrument scheduling in satellite based on available battery charge
  4. Multimedia SoC power gating structure

Reports and Analysis

  1. Report: Instantaneous power, average power and battery discharge
  2. Analysis: Latency vs. Power Consumed metrics and power per memory access

 

Read More about VisualSim Power Modeling and Analysis 

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