Model-based System Architecture
Provides a virtual exploration platform for cyber-physical systems. Bridges the product development gap by extending the SysML model with timing, power and functionality. Enables systems engineers and product architects to work concurrently with the same model and at the same abstraction-levels.
Electronic System-Level Design
Platform to explore hardware-software partitioning, bus topology design, cache-memory hierarchy design, multi-core architectures. Can model analog, digital, IP, processor, GPU, memory/cache, bus, and interfaces. Platform, firmware, mixed-signal and system architects can work together.
Performance, Functional and Failure Analysis
Conduct stochastic, monte-carlo and cycle-accurate exploration to measure the latency, throughput and utilization. Used to validate the specification, generate the requirements and provide traces for downstream verification. Enable multi-level abstraction modeling and simulate with use-cases and real-life workloads.
System-Level Power Exploration
Prototype all aspects of the power system including generators to batteries and the power management algorithms at the IP, semiconductors, board, system and network-levels. Measure the peak current, average consumption per block, battery discharge, capacity requirements, charging rates and battery life.